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@@ -1,7 +1,7 @@
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/**
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* @file AD7124_ATY.c
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*
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-* @param Project DEVICE_GENERAL_ATY_LIB
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+* @param Project DEVICE_DRIVER_ATY_LIB
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*
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* @author ATY
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*
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@@ -18,6 +18,8 @@
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*
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* @brief functions of AD7124 for C platform
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*
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+* @note SPI_POLARITY_LOW + SPI_PHASE_1EDGE = CPOL=0, CPHA=0 = SPI Mode 1
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+*
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* @version
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* - 1_01_230828 > ATY
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* -# Preliminary version, first Release
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@@ -27,6 +29,8 @@
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* -# add lock
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* - 1_04_251124 > ATY
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* -# change log and test basely
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+* - 1_05_251225 > ATY
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+* -# change dev position and add initFlag to auto init
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********************************************************************************
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*/
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@@ -48,13 +52,14 @@
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* @param dev
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* @return uint8_t
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*/
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-uint8_t AD7124_WriteRead(uint8_t* data, uint8_t len, struct AD7124_ATY_Dev* dev){
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+uint8_t AD7124_WriteRead(struct AD7124_ATY_Dev* dev, uint8_t* data, uint8_t len){
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uint8_t errCode = 0;
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+
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__ATY_LOCK(dev);
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dev->nssSet(__ATY_HL_L);
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printf_ATY_D("%sRW_W: ", AD7124_ATY_TAG);
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for(int i = 0; i < len; i++) printf_ATY_D("%02X ", data[i]);
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- errCode = dev->spiProcess(data, len, __ATY_RW_RW);
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+ errCode = dev->spiProcess(data, len);
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printf_ATY_D("%sRW_R: ", AD7124_ATY_TAG);
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for(int i = 0; i < len; i++) printf_ATY_D("%02X ", data[i]);
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dev->nssSet(__ATY_HL_H);
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@@ -80,7 +85,7 @@ uint8_t AD7124_Reset(struct AD7124_ATY_Dev* dev){
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__ATY_UNLOCK(dev);
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// write more than 64 bits to reset AD7124
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- errCode = AD7124_WriteRead(resetBuf, 9, dev);
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+ errCode = AD7124_WriteRead(dev, resetBuf, 9);
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return errCode;
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}
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@@ -91,12 +96,12 @@ uint8_t AD7124_Reset(struct AD7124_ATY_Dev* dev){
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* @param dev
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* @return uint8_t
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*/
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-uint8_t AD7124_ReadId(uint8_t* id, struct AD7124_ATY_Dev* dev){
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+uint8_t AD7124_ReadId(struct AD7124_ATY_Dev* dev, uint8_t* id){
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uint8_t errCode = 0, groupTrans[2] = {0};
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printf_ATY_D("%s--ReadId", AD7124_ATY_TAG);
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groupTrans[0] = 0x45;
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groupTrans[1] = 0;
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- errCode = AD7124_WriteRead(groupTrans, 2, dev);
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+ errCode = AD7124_WriteRead(dev, groupTrans, 2);
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dev->id = groupTrans[1];
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*id = dev->id;
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printf_ATY_D("%sAD7124_ID: %02X\r\n", AD7124_ATY_TAG, dev->id);
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@@ -113,7 +118,7 @@ uint8_t AD7124_ReadId(uint8_t* id, struct AD7124_ATY_Dev* dev){
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* @return uint8_t
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* @note AD7124_ERR_REG_SPI_IGNORE_ERR only for crc trans
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*/
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-uint8_t AD7124_WriteReg(uint8_t regAddr, uint32_t data, uint8_t len, struct AD7124_ATY_Dev* dev){
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+uint8_t AD7124_WriteReg(struct AD7124_ATY_Dev* dev, uint8_t regAddr, uint32_t data, uint8_t len){
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uint8_t errCode = 0, i = 0, groupTrans[4] = {0};
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printf_ATY_D("%s--WriteReg", AD7124_ATY_TAG);
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groupTrans[0] = AD7124_COMM_REG_WA(regAddr);
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@@ -124,7 +129,7 @@ uint8_t AD7124_WriteReg(uint8_t regAddr, uint32_t data, uint8_t len, struct AD71
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printf_ATY_D("%sWriteReg: ", AD7124_ATY_TAG);
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for(i = 0; i < len + 1; i++)
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printf_ATY_D("%02X ", groupTrans[i]);
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- errCode = AD7124_WriteRead(groupTrans, len + 1, dev);
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+ errCode = AD7124_WriteRead(dev, groupTrans, len + 1);
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return errCode;
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}
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@@ -137,11 +142,11 @@ uint8_t AD7124_WriteReg(uint8_t regAddr, uint32_t data, uint8_t len, struct AD71
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* @param dev
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* @return uint8_t
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*/
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-uint8_t AD7124_ReadReg(uint8_t regAddr, uint32_t* data, uint8_t len, struct AD7124_ATY_Dev* dev){
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+uint8_t AD7124_ReadReg(struct AD7124_ATY_Dev* dev, uint8_t regAddr, uint32_t* data, uint8_t len){
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uint8_t errCode = 0, i = 0, groupTrans[4] = {0};
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printf_ATY_D("%s--ReadReg", AD7124_ATY_TAG);
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groupTrans[0] = AD7124_COMM_REG_RA(regAddr);
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- errCode = AD7124_WriteRead(groupTrans, len + 1, dev);
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+ errCode = AD7124_WriteRead(dev, groupTrans, len + 1);
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if(len == 1)
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*data = groupTrans[1];
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else if(len == 2)
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@@ -161,11 +166,14 @@ uint8_t AD7124_ReadReg(uint8_t regAddr, uint32_t* data, uint8_t len, struct AD71
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* @param dev
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* @return uint8_t
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*/
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-uint8_t AD7124_ReadData(uint8_t* data, struct AD7124_ATY_Dev* dev){
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+uint8_t AD7124_ReadData(struct AD7124_ATY_Dev* dev, uint8_t* data){
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+ AD7124_Init(dev, dev->cfg);
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+
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printf_ATY_D("%s--ReadData", AD7124_ATY_TAG);
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uint8_t errCode = 0, i = 0;
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data[0] = AD7124_COMM_REG_RA(AD7124_DATA_REG);
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- errCode = AD7124_WriteRead(data, 5, dev);
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+ errCode = AD7124_WriteRead(dev, data, 5);
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+
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printf_ATY_D("%sReadData: 0x ", AD7124_ATY_TAG);
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for(i = 0; i < 5; i++)
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printf_ATY_D("%02X ", data[i]);
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@@ -179,9 +187,9 @@ uint8_t AD7124_ReadData(uint8_t* data, struct AD7124_ATY_Dev* dev){
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* @param dev
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* @return uint8_t
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*/
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-uint8_t AD7124_ReadStatus(uint8_t* status, struct AD7124_ATY_Dev* dev){
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+uint8_t AD7124_ReadStatus(struct AD7124_ATY_Dev* dev, uint8_t* status){
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printf_ATY_D("%s--ReadStatus", AD7124_ATY_TAG);
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- if(AD7124_ReadReg(AD7124_STATUS_REG, (uint32_t*)status, 1, dev)){
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+ if(AD7124_ReadReg(dev, AD7124_STATUS_REG, (uint32_t*)status, 1)){
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printf_ATY_D("%sAD7124_ERR: STATE %02X %02X\r\n",
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AD7124_ATY_TAG, status[0], status[1]);
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return 1;
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@@ -224,24 +232,29 @@ float AD7124_DataToResDefault(uint32_t data){
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* @param dev
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* @return uint8_t
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*/
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-uint8_t AD7124_Init(struct AD7124_ATY_Cfg* cfg, struct AD7124_ATY_Dev* dev){
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- uint8_t id = 0, status[2] = {0};
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- dev->enSet(__ATY_HL_H);
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- if(AD7124_Reset(dev)){
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- printf_ATY_D("%sAD7124_ERR: RST\r\n", AD7124_ATY_TAG);
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- return 1;
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- }
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- if(AD7124_ReadId(&id, dev)){
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- printf_ATY_D("%sAD7124_ERR: ID\r\n", AD7124_ATY_TAG);
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- return 2;
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- }
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- if(AD7124_ReadStatus(status, dev)){
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- printf_ATY_D("%sAD7124_ERR: Status\r\n", AD7124_ATY_TAG);
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- return 3;
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- }
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- if(AD7124_Config(cfg, dev)){
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- printf_ATY_D("%sAD7124_ERR: CFG\r\n", AD7124_ATY_TAG);
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- return 4;
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+uint8_t AD7124_Init(struct AD7124_ATY_Dev* dev, struct AD7124_ATY_Cfg* cfg){
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+ if(dev->initFlag == 0){
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+ uint8_t id = 0, status[2] = {0};
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+ printf_ATY_D("%sAD7124_Init", AD7124_ATY_TAG);
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+ dev->enSet(__ATY_HL_H);
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+ if(AD7124_Reset(dev)){
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+ printf_ATY_D("%sAD7124_ERR: RST", AD7124_ATY_TAG);
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+ return 1;
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+ }
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+ if(AD7124_ReadId(dev, &id)){
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+ printf_ATY_D("%sAD7124_ERR: ID", AD7124_ATY_TAG);
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+ return 2;
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+ }
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+ if(AD7124_ReadStatus(dev, status)){
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+ printf_ATY_D("%sAD7124_ERR: Status", AD7124_ATY_TAG);
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+ return 3;
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+ }
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+ if(AD7124_Config(dev, cfg)){
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+ printf_ATY_D("%sAD7124_ERR: CFG", AD7124_ATY_TAG);
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+ return 4;
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+ }
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+ dev->initFlag = 1;
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+ return 0;
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}
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return 0;
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}
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@@ -253,65 +266,65 @@ uint8_t AD7124_Init(struct AD7124_ATY_Cfg* cfg, struct AD7124_ATY_Dev* dev){
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* @param dev
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* @return uint8_t
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*/
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-uint8_t AD7124_Config(struct AD7124_ATY_Cfg* cfg, struct AD7124_ATY_Dev* dev){
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+uint8_t AD7124_Config(struct AD7124_ATY_Dev* dev, struct AD7124_ATY_Cfg* cfg){
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printf_ATY_D("%s--Config", AD7124_ATY_TAG);
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- if(cfg->AD7124_ADC_CTRL_REG_t) AD7124_WriteReg(AD7124_ADC_CTRL_REG, cfg->AD7124_ADC_CTRL_REG_t, 2, dev);
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- if(cfg->AD7124_IO_CTRL1_REG_t) AD7124_WriteReg(AD7124_IO_CTRL1_REG, cfg->AD7124_IO_CTRL1_REG_t, 3, dev);
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- if(cfg->AD7124_IO_CTRL2_REG_t) AD7124_WriteReg(AD7124_IO_CTRL2_REG, cfg->AD7124_IO_CTRL2_REG_t, 2, dev);
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- if(cfg->AD7124_ERREN_REG_t) AD7124_WriteReg(AD7124_ERREN_REG, cfg->AD7124_ERREN_REG_t, 3, dev);
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-
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- if(cfg->AD7124_CH0_MAP_REG_t) AD7124_WriteReg(AD7124_CH0_MAP_REG, cfg->AD7124_CH0_MAP_REG_t, 2, dev);
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- if(cfg->AD7124_CH1_MAP_REG_t) AD7124_WriteReg(AD7124_CH1_MAP_REG, cfg->AD7124_CH1_MAP_REG_t, 2, dev);
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- if(cfg->AD7124_CH2_MAP_REG_t) AD7124_WriteReg(AD7124_CH2_MAP_REG, cfg->AD7124_CH2_MAP_REG_t, 2, dev);
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- if(cfg->AD7124_CH3_MAP_REG_t) AD7124_WriteReg(AD7124_CH3_MAP_REG, cfg->AD7124_CH3_MAP_REG_t, 2, dev);
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- if(cfg->AD7124_CH4_MAP_REG_t) AD7124_WriteReg(AD7124_CH4_MAP_REG, cfg->AD7124_CH4_MAP_REG_t, 2, dev);
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- if(cfg->AD7124_CH5_MAP_REG_t) AD7124_WriteReg(AD7124_CH5_MAP_REG, cfg->AD7124_CH5_MAP_REG_t, 2, dev);
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- if(cfg->AD7124_CH6_MAP_REG_t) AD7124_WriteReg(AD7124_CH6_MAP_REG, cfg->AD7124_CH6_MAP_REG_t, 2, dev);
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- if(cfg->AD7124_CH7_MAP_REG_t) AD7124_WriteReg(AD7124_CH7_MAP_REG, cfg->AD7124_CH7_MAP_REG_t, 2, dev);
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- if(cfg->AD7124_CH8_MAP_REG_t) AD7124_WriteReg(AD7124_CH8_MAP_REG, cfg->AD7124_CH8_MAP_REG_t, 2, dev);
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- if(cfg->AD7124_CH9_MAP_REG_t) AD7124_WriteReg(AD7124_CH9_MAP_REG, cfg->AD7124_CH9_MAP_REG_t, 2, dev);
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- if(cfg->AD7124_CH10_MAP_REG_t) AD7124_WriteReg(AD7124_CH10_MAP_REG, cfg->AD7124_CH10_MAP_REG_t, 2, dev);
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- if(cfg->AD7124_CH11_MAP_REG_t) AD7124_WriteReg(AD7124_CH11_MAP_REG, cfg->AD7124_CH11_MAP_REG_t, 2, dev);
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- if(cfg->AD7124_CH12_MAP_REG_t) AD7124_WriteReg(AD7124_CH12_MAP_REG, cfg->AD7124_CH12_MAP_REG_t, 2, dev);
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- if(cfg->AD7124_CH13_MAP_REG_t) AD7124_WriteReg(AD7124_CH13_MAP_REG, cfg->AD7124_CH13_MAP_REG_t, 2, dev);
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- if(cfg->AD7124_CH14_MAP_REG_t) AD7124_WriteReg(AD7124_CH14_MAP_REG, cfg->AD7124_CH14_MAP_REG_t, 2, dev);
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- if(cfg->AD7124_CH15_MAP_REG_t) AD7124_WriteReg(AD7124_CH15_MAP_REG, cfg->AD7124_CH15_MAP_REG_t, 2, dev);
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-
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- if(cfg->AD7124_CFG0_REG_t) AD7124_WriteReg(AD7124_CFG0_REG, cfg->AD7124_CFG0_REG_t, 2, dev);
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- if(cfg->AD7124_CFG1_REG_t) AD7124_WriteReg(AD7124_CFG1_REG, cfg->AD7124_CFG1_REG_t, 2, dev);
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- if(cfg->AD7124_CFG2_REG_t) AD7124_WriteReg(AD7124_CFG2_REG, cfg->AD7124_CFG2_REG_t, 2, dev);
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- if(cfg->AD7124_CFG3_REG_t) AD7124_WriteReg(AD7124_CFG3_REG, cfg->AD7124_CFG3_REG_t, 2, dev);
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- if(cfg->AD7124_CFG4_REG_t) AD7124_WriteReg(AD7124_CFG4_REG, cfg->AD7124_CFG4_REG_t, 2, dev);
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- if(cfg->AD7124_CFG5_REG_t) AD7124_WriteReg(AD7124_CFG5_REG, cfg->AD7124_CFG5_REG_t, 2, dev);
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- if(cfg->AD7124_CFG6_REG_t) AD7124_WriteReg(AD7124_CFG6_REG, cfg->AD7124_CFG6_REG_t, 2, dev);
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- if(cfg->AD7124_CFG7_REG_t) AD7124_WriteReg(AD7124_CFG7_REG, cfg->AD7124_CFG7_REG_t, 2, dev);
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-
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- if(cfg->AD7124_FILT0_REG_t) AD7124_WriteReg(AD7124_FILT0_REG, cfg->AD7124_FILT0_REG_t, 3, dev);
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- if(cfg->AD7124_FILT1_REG_t) AD7124_WriteReg(AD7124_FILT1_REG, cfg->AD7124_FILT1_REG_t, 3, dev);
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- if(cfg->AD7124_FILT2_REG_t) AD7124_WriteReg(AD7124_FILT2_REG, cfg->AD7124_FILT2_REG_t, 3, dev);
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- if(cfg->AD7124_FILT3_REG_t) AD7124_WriteReg(AD7124_FILT3_REG, cfg->AD7124_FILT3_REG_t, 3, dev);
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- if(cfg->AD7124_FILT4_REG_t) AD7124_WriteReg(AD7124_FILT4_REG, cfg->AD7124_FILT4_REG_t, 3, dev);
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- if(cfg->AD7124_FILT5_REG_t) AD7124_WriteReg(AD7124_FILT5_REG, cfg->AD7124_FILT5_REG_t, 3, dev);
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- if(cfg->AD7124_FILT6_REG_t) AD7124_WriteReg(AD7124_FILT6_REG, cfg->AD7124_FILT6_REG_t, 3, dev);
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- if(cfg->AD7124_FILT7_REG_t) AD7124_WriteReg(AD7124_FILT7_REG, cfg->AD7124_FILT7_REG_t, 3, dev);
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-
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- if(cfg->AD7124_OFFS0_REG_t) AD7124_WriteReg(AD7124_OFFS0_REG, cfg->AD7124_OFFS0_REG_t, 3, dev);
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- if(cfg->AD7124_OFFS1_REG_t) AD7124_WriteReg(AD7124_OFFS1_REG, cfg->AD7124_OFFS1_REG_t, 3, dev);
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- if(cfg->AD7124_OFFS2_REG_t) AD7124_WriteReg(AD7124_OFFS2_REG, cfg->AD7124_OFFS2_REG_t, 3, dev);
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- if(cfg->AD7124_OFFS3_REG_t) AD7124_WriteReg(AD7124_OFFS3_REG, cfg->AD7124_OFFS3_REG_t, 3, dev);
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- if(cfg->AD7124_OFFS4_REG_t) AD7124_WriteReg(AD7124_OFFS4_REG, cfg->AD7124_OFFS4_REG_t, 3, dev);
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- if(cfg->AD7124_OFFS5_REG_t) AD7124_WriteReg(AD7124_OFFS5_REG, cfg->AD7124_OFFS5_REG_t, 3, dev);
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- if(cfg->AD7124_OFFS6_REG_t) AD7124_WriteReg(AD7124_OFFS6_REG, cfg->AD7124_OFFS6_REG_t, 3, dev);
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- if(cfg->AD7124_OFFS7_REG_t) AD7124_WriteReg(AD7124_OFFS7_REG, cfg->AD7124_OFFS7_REG_t, 3, dev);
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-
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- if(cfg->AD7124_GAIN0_REG_t) AD7124_WriteReg(AD7124_GAIN0_REG, cfg->AD7124_GAIN0_REG_t, 3, dev);
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- if(cfg->AD7124_GAIN1_REG_t) AD7124_WriteReg(AD7124_GAIN1_REG, cfg->AD7124_GAIN1_REG_t, 3, dev);
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- if(cfg->AD7124_GAIN2_REG_t) AD7124_WriteReg(AD7124_GAIN2_REG, cfg->AD7124_GAIN2_REG_t, 3, dev);
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- if(cfg->AD7124_GAIN3_REG_t) AD7124_WriteReg(AD7124_GAIN3_REG, cfg->AD7124_GAIN3_REG_t, 3, dev);
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- if(cfg->AD7124_GAIN4_REG_t) AD7124_WriteReg(AD7124_GAIN4_REG, cfg->AD7124_GAIN4_REG_t, 3, dev);
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- if(cfg->AD7124_GAIN5_REG_t) AD7124_WriteReg(AD7124_GAIN5_REG, cfg->AD7124_GAIN5_REG_t, 3, dev);
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- if(cfg->AD7124_GAIN6_REG_t) AD7124_WriteReg(AD7124_GAIN6_REG, cfg->AD7124_GAIN6_REG_t, 3, dev);
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- if(cfg->AD7124_GAIN7_REG_t) AD7124_WriteReg(AD7124_GAIN7_REG, cfg->AD7124_GAIN7_REG_t, 3, dev);
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+ if(cfg->AD7124_ADC_CTRL_REG_t) AD7124_WriteReg(dev, AD7124_ADC_CTRL_REG, cfg->AD7124_ADC_CTRL_REG_t, 2);
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+ if(cfg->AD7124_IO_CTRL1_REG_t) AD7124_WriteReg(dev, AD7124_IO_CTRL1_REG, cfg->AD7124_IO_CTRL1_REG_t, 3);
|
|
|
+ if(cfg->AD7124_IO_CTRL2_REG_t) AD7124_WriteReg(dev, AD7124_IO_CTRL2_REG, cfg->AD7124_IO_CTRL2_REG_t, 2);
|
|
|
+ if(cfg->AD7124_ERREN_REG_t) AD7124_WriteReg(dev, AD7124_ERREN_REG, cfg->AD7124_ERREN_REG_t, 3);
|
|
|
+
|
|
|
+ if(cfg->AD7124_CH0_MAP_REG_t) AD7124_WriteReg(dev, AD7124_CH0_MAP_REG, cfg->AD7124_CH0_MAP_REG_t, 2);
|
|
|
+ if(cfg->AD7124_CH1_MAP_REG_t) AD7124_WriteReg(dev, AD7124_CH1_MAP_REG, cfg->AD7124_CH1_MAP_REG_t, 2);
|
|
|
+ if(cfg->AD7124_CH2_MAP_REG_t) AD7124_WriteReg(dev, AD7124_CH2_MAP_REG, cfg->AD7124_CH2_MAP_REG_t, 2);
|
|
|
+ if(cfg->AD7124_CH3_MAP_REG_t) AD7124_WriteReg(dev, AD7124_CH3_MAP_REG, cfg->AD7124_CH3_MAP_REG_t, 2);
|
|
|
+ if(cfg->AD7124_CH4_MAP_REG_t) AD7124_WriteReg(dev, AD7124_CH4_MAP_REG, cfg->AD7124_CH4_MAP_REG_t, 2);
|
|
|
+ if(cfg->AD7124_CH5_MAP_REG_t) AD7124_WriteReg(dev, AD7124_CH5_MAP_REG, cfg->AD7124_CH5_MAP_REG_t, 2);
|
|
|
+ if(cfg->AD7124_CH6_MAP_REG_t) AD7124_WriteReg(dev, AD7124_CH6_MAP_REG, cfg->AD7124_CH6_MAP_REG_t, 2);
|
|
|
+ if(cfg->AD7124_CH7_MAP_REG_t) AD7124_WriteReg(dev, AD7124_CH7_MAP_REG, cfg->AD7124_CH7_MAP_REG_t, 2);
|
|
|
+ if(cfg->AD7124_CH8_MAP_REG_t) AD7124_WriteReg(dev, AD7124_CH8_MAP_REG, cfg->AD7124_CH8_MAP_REG_t, 2);
|
|
|
+ if(cfg->AD7124_CH9_MAP_REG_t) AD7124_WriteReg(dev, AD7124_CH9_MAP_REG, cfg->AD7124_CH9_MAP_REG_t, 2);
|
|
|
+ if(cfg->AD7124_CH10_MAP_REG_t) AD7124_WriteReg(dev, AD7124_CH10_MAP_REG, cfg->AD7124_CH10_MAP_REG_t, 2);
|
|
|
+ if(cfg->AD7124_CH11_MAP_REG_t) AD7124_WriteReg(dev, AD7124_CH11_MAP_REG, cfg->AD7124_CH11_MAP_REG_t, 2);
|
|
|
+ if(cfg->AD7124_CH12_MAP_REG_t) AD7124_WriteReg(dev, AD7124_CH12_MAP_REG, cfg->AD7124_CH12_MAP_REG_t, 2);
|
|
|
+ if(cfg->AD7124_CH13_MAP_REG_t) AD7124_WriteReg(dev, AD7124_CH13_MAP_REG, cfg->AD7124_CH13_MAP_REG_t, 2);
|
|
|
+ if(cfg->AD7124_CH14_MAP_REG_t) AD7124_WriteReg(dev, AD7124_CH14_MAP_REG, cfg->AD7124_CH14_MAP_REG_t, 2);
|
|
|
+ if(cfg->AD7124_CH15_MAP_REG_t) AD7124_WriteReg(dev, AD7124_CH15_MAP_REG, cfg->AD7124_CH15_MAP_REG_t, 2);
|
|
|
+
|
|
|
+ if(cfg->AD7124_CFG0_REG_t) AD7124_WriteReg(dev, AD7124_CFG0_REG, cfg->AD7124_CFG0_REG_t, 2);
|
|
|
+ if(cfg->AD7124_CFG1_REG_t) AD7124_WriteReg(dev, AD7124_CFG1_REG, cfg->AD7124_CFG1_REG_t, 2);
|
|
|
+ if(cfg->AD7124_CFG2_REG_t) AD7124_WriteReg(dev, AD7124_CFG2_REG, cfg->AD7124_CFG2_REG_t, 2);
|
|
|
+ if(cfg->AD7124_CFG3_REG_t) AD7124_WriteReg(dev, AD7124_CFG3_REG, cfg->AD7124_CFG3_REG_t, 2);
|
|
|
+ if(cfg->AD7124_CFG4_REG_t) AD7124_WriteReg(dev, AD7124_CFG4_REG, cfg->AD7124_CFG4_REG_t, 2);
|
|
|
+ if(cfg->AD7124_CFG5_REG_t) AD7124_WriteReg(dev, AD7124_CFG5_REG, cfg->AD7124_CFG5_REG_t, 2);
|
|
|
+ if(cfg->AD7124_CFG6_REG_t) AD7124_WriteReg(dev, AD7124_CFG6_REG, cfg->AD7124_CFG6_REG_t, 2);
|
|
|
+ if(cfg->AD7124_CFG7_REG_t) AD7124_WriteReg(dev, AD7124_CFG7_REG, cfg->AD7124_CFG7_REG_t, 2);
|
|
|
+
|
|
|
+ if(cfg->AD7124_FILT0_REG_t) AD7124_WriteReg(dev, AD7124_FILT0_REG, cfg->AD7124_FILT0_REG_t, 3);
|
|
|
+ if(cfg->AD7124_FILT1_REG_t) AD7124_WriteReg(dev, AD7124_FILT1_REG, cfg->AD7124_FILT1_REG_t, 3);
|
|
|
+ if(cfg->AD7124_FILT2_REG_t) AD7124_WriteReg(dev, AD7124_FILT2_REG, cfg->AD7124_FILT2_REG_t, 3);
|
|
|
+ if(cfg->AD7124_FILT3_REG_t) AD7124_WriteReg(dev, AD7124_FILT3_REG, cfg->AD7124_FILT3_REG_t, 3);
|
|
|
+ if(cfg->AD7124_FILT4_REG_t) AD7124_WriteReg(dev, AD7124_FILT4_REG, cfg->AD7124_FILT4_REG_t, 3);
|
|
|
+ if(cfg->AD7124_FILT5_REG_t) AD7124_WriteReg(dev, AD7124_FILT5_REG, cfg->AD7124_FILT5_REG_t, 3);
|
|
|
+ if(cfg->AD7124_FILT6_REG_t) AD7124_WriteReg(dev, AD7124_FILT6_REG, cfg->AD7124_FILT6_REG_t, 3);
|
|
|
+ if(cfg->AD7124_FILT7_REG_t) AD7124_WriteReg(dev, AD7124_FILT7_REG, cfg->AD7124_FILT7_REG_t, 3);
|
|
|
+
|
|
|
+ if(cfg->AD7124_OFFS0_REG_t) AD7124_WriteReg(dev, AD7124_OFFS0_REG, cfg->AD7124_OFFS0_REG_t, 3);
|
|
|
+ if(cfg->AD7124_OFFS1_REG_t) AD7124_WriteReg(dev, AD7124_OFFS1_REG, cfg->AD7124_OFFS1_REG_t, 3);
|
|
|
+ if(cfg->AD7124_OFFS2_REG_t) AD7124_WriteReg(dev, AD7124_OFFS2_REG, cfg->AD7124_OFFS2_REG_t, 3);
|
|
|
+ if(cfg->AD7124_OFFS3_REG_t) AD7124_WriteReg(dev, AD7124_OFFS3_REG, cfg->AD7124_OFFS3_REG_t, 3);
|
|
|
+ if(cfg->AD7124_OFFS4_REG_t) AD7124_WriteReg(dev, AD7124_OFFS4_REG, cfg->AD7124_OFFS4_REG_t, 3);
|
|
|
+ if(cfg->AD7124_OFFS5_REG_t) AD7124_WriteReg(dev, AD7124_OFFS5_REG, cfg->AD7124_OFFS5_REG_t, 3);
|
|
|
+ if(cfg->AD7124_OFFS6_REG_t) AD7124_WriteReg(dev, AD7124_OFFS6_REG, cfg->AD7124_OFFS6_REG_t, 3);
|
|
|
+ if(cfg->AD7124_OFFS7_REG_t) AD7124_WriteReg(dev, AD7124_OFFS7_REG, cfg->AD7124_OFFS7_REG_t, 3);
|
|
|
+
|
|
|
+ if(cfg->AD7124_GAIN0_REG_t) AD7124_WriteReg(dev, AD7124_GAIN0_REG, cfg->AD7124_GAIN0_REG_t, 3);
|
|
|
+ if(cfg->AD7124_GAIN1_REG_t) AD7124_WriteReg(dev, AD7124_GAIN1_REG, cfg->AD7124_GAIN1_REG_t, 3);
|
|
|
+ if(cfg->AD7124_GAIN2_REG_t) AD7124_WriteReg(dev, AD7124_GAIN2_REG, cfg->AD7124_GAIN2_REG_t, 3);
|
|
|
+ if(cfg->AD7124_GAIN3_REG_t) AD7124_WriteReg(dev, AD7124_GAIN3_REG, cfg->AD7124_GAIN3_REG_t, 3);
|
|
|
+ if(cfg->AD7124_GAIN4_REG_t) AD7124_WriteReg(dev, AD7124_GAIN4_REG, cfg->AD7124_GAIN4_REG_t, 3);
|
|
|
+ if(cfg->AD7124_GAIN5_REG_t) AD7124_WriteReg(dev, AD7124_GAIN5_REG, cfg->AD7124_GAIN5_REG_t, 3);
|
|
|
+ if(cfg->AD7124_GAIN6_REG_t) AD7124_WriteReg(dev, AD7124_GAIN6_REG, cfg->AD7124_GAIN6_REG_t, 3);
|
|
|
+ if(cfg->AD7124_GAIN7_REG_t) AD7124_WriteReg(dev, AD7124_GAIN7_REG, cfg->AD7124_GAIN7_REG_t, 3);
|
|
|
|
|
|
printf_ATY_D("\r\n");
|
|
|
return 0;
|
|
|
@@ -329,44 +342,46 @@ uint8_t AD7124_Config(struct AD7124_ATY_Cfg* cfg, struct AD7124_ATY_Dev* dev){
|
|
|
0100 sys full cal
|
|
|
1000 sys zero cal
|
|
|
*/
|
|
|
-uint8_t AD7124_Calibrate(uint8_t calibrateType, struct AD7124_ATY_Cfg* cfg, struct AD7124_ATY_Dev* dev){
|
|
|
+uint8_t AD7124_Calibrate(struct AD7124_ATY_Dev* dev, struct AD7124_ATY_Cfg* cfg, uint8_t calibrateType){
|
|
|
uint32_t regTrans = 0;
|
|
|
+ AD7124_Init(dev, dev->cfg);
|
|
|
+
|
|
|
printf_ATY_D("%s--Calibrate: %02X", AD7124_ATY_TAG, calibrateType);
|
|
|
- AD7124_WriteReg(AD7124_OFFS0_REG, 0x800000, 3, dev);
|
|
|
- AD7124_WriteReg(AD7124_OFFS1_REG, 0x800000, 3, dev);
|
|
|
- AD7124_WriteReg(AD7124_OFFS2_REG, 0x800000, 3, dev);
|
|
|
- AD7124_WriteReg(AD7124_OFFS3_REG, 0x800000, 3, dev);
|
|
|
- AD7124_WriteReg(AD7124_OFFS4_REG, 0x800000, 3, dev);
|
|
|
- AD7124_WriteReg(AD7124_OFFS5_REG, 0x800000, 3, dev);
|
|
|
- AD7124_WriteReg(AD7124_OFFS6_REG, 0x800000, 3, dev);
|
|
|
- AD7124_WriteReg(AD7124_OFFS7_REG, 0x800000, 3, dev);
|
|
|
+ AD7124_WriteReg(dev, AD7124_OFFS0_REG, 0x800000, 3);
|
|
|
+ AD7124_WriteReg(dev, AD7124_OFFS1_REG, 0x800000, 3);
|
|
|
+ AD7124_WriteReg(dev, AD7124_OFFS2_REG, 0x800000, 3);
|
|
|
+ AD7124_WriteReg(dev, AD7124_OFFS3_REG, 0x800000, 3);
|
|
|
+ AD7124_WriteReg(dev, AD7124_OFFS4_REG, 0x800000, 3);
|
|
|
+ AD7124_WriteReg(dev, AD7124_OFFS5_REG, 0x800000, 3);
|
|
|
+ AD7124_WriteReg(dev, AD7124_OFFS6_REG, 0x800000, 3);
|
|
|
+ AD7124_WriteReg(dev, AD7124_OFFS7_REG, 0x800000, 3);
|
|
|
|
|
|
if(calibrateType & AD7124_CALIBRATE_INT_FULL){
|
|
|
- AD7124_WriteReg(AD7124_ADC_CTRL_REG, 0x0058, 2, dev); // int full cal at mid power
|
|
|
- AD7124_ReadReg(AD7124_ADC_CTRL_REG, ®Trans, 2, dev);
|
|
|
+ AD7124_WriteReg(dev, AD7124_ADC_CTRL_REG, 0x0058, 2); // int full cal at mid power
|
|
|
+ AD7124_ReadReg(dev, AD7124_ADC_CTRL_REG, ®Trans, 2);
|
|
|
dev->delay(1500); // 1300ms min
|
|
|
- AD7124_ReadReg(AD7124_ADC_CTRL_REG, ®Trans, 2, dev);
|
|
|
+ AD7124_ReadReg(dev, AD7124_ADC_CTRL_REG, ®Trans, 2);
|
|
|
}
|
|
|
if(calibrateType & AD7124_CALIBRATE_INT_ZERO){
|
|
|
- AD7124_WriteReg(AD7124_ADC_CTRL_REG, 0x0094, 2, dev); // int zero cal at full power
|
|
|
- AD7124_ReadReg(AD7124_ADC_CTRL_REG, ®Trans, 2, dev);
|
|
|
+ AD7124_WriteReg(dev, AD7124_ADC_CTRL_REG, 0x0094, 2); // int zero cal at full power
|
|
|
+ AD7124_ReadReg(dev, AD7124_ADC_CTRL_REG, ®Trans, 2);
|
|
|
dev->delay(100); // 80ms min
|
|
|
- AD7124_ReadReg(AD7124_ADC_CTRL_REG, ®Trans, 2, dev);
|
|
|
+ AD7124_ReadReg(dev, AD7124_ADC_CTRL_REG, ®Trans, 2);
|
|
|
}
|
|
|
if(calibrateType & AD7124_CALIBRATE_SYS_FULL){
|
|
|
- AD7124_WriteReg(AD7124_ADC_CTRL_REG, 0x00A0, 2, dev); // sys full cal
|
|
|
- AD7124_ReadReg(AD7124_ADC_CTRL_REG, ®Trans, 2, dev);
|
|
|
+ AD7124_WriteReg(dev, AD7124_ADC_CTRL_REG, 0x00A0, 2); // sys full cal
|
|
|
+ AD7124_ReadReg(dev, AD7124_ADC_CTRL_REG, ®Trans, 2);
|
|
|
dev->delay(100); // 80ms min
|
|
|
- AD7124_ReadReg(AD7124_ADC_CTRL_REG, ®Trans, 2, dev);
|
|
|
+ AD7124_ReadReg(dev, AD7124_ADC_CTRL_REG, ®Trans, 2);
|
|
|
}
|
|
|
if(calibrateType & AD7124_CALIBRATE_SYS_ZERO){
|
|
|
- AD7124_WriteReg(AD7124_ADC_CTRL_REG, 0x009C, 2, dev); // sys zero cal
|
|
|
- AD7124_ReadReg(AD7124_ADC_CTRL_REG, ®Trans, 2, dev);
|
|
|
+ AD7124_WriteReg(dev, AD7124_ADC_CTRL_REG, 0x009C, 2); // sys zero cal
|
|
|
+ AD7124_ReadReg(dev, AD7124_ADC_CTRL_REG, ®Trans, 2);
|
|
|
dev->delay(100); // 80ms min
|
|
|
- AD7124_ReadReg(AD7124_ADC_CTRL_REG, ®Trans, 2, dev);
|
|
|
+ AD7124_ReadReg(dev, AD7124_ADC_CTRL_REG, ®Trans, 2);
|
|
|
}
|
|
|
|
|
|
- AD7124_WriteReg(AD7124_ADC_CTRL_REG, cfg->AD7124_ADC_CTRL_REG_t, 2, dev); // detect mode
|
|
|
+ AD7124_WriteReg(dev, AD7124_ADC_CTRL_REG, cfg->AD7124_ADC_CTRL_REG_t, 2); // detect mode
|
|
|
printf_ATY_D("\r\n");
|
|
|
dev->delay(1);
|
|
|
return 0;
|
|
|
@@ -378,13 +393,13 @@ uint8_t AD7124_Calibrate(uint8_t calibrateType, struct AD7124_ATY_Cfg* cfg, stru
|
|
|
* @param dev
|
|
|
* @return uint8_t
|
|
|
*/
|
|
|
-uint8_t AD7124_ReadAllReg(struct AD7124_ATY_Cfg* cfg, struct AD7124_ATY_Dev* dev){
|
|
|
+uint8_t AD7124_ReadAllReg(struct AD7124_ATY_Dev* dev, struct AD7124_ATY_Cfg* cfg){
|
|
|
uint8_t i = 0;
|
|
|
uint32_t* p = (uint32_t*)cfg;
|
|
|
printf_ATY_D("%s--AllRegs %d", AD7124_ATY_TAG, (sizeof(struct AD7124_ATY_Cfg) / sizeof(uint32_t)));
|
|
|
for(i = 0; i < (sizeof(struct AD7124_ATY_Cfg) / sizeof(uint32_t)); i++){ // 0x00~0x38
|
|
|
printf_ATY_D("\r\nReg 0x%02X: ", i);
|
|
|
- AD7124_ReadReg(i, (p + i), 3, dev);
|
|
|
+ AD7124_ReadReg(dev, i, (p + i), 3);
|
|
|
}
|
|
|
// AD7124_ReadReg(AD7124_ADC_CTRL_REG, groupTrans, 2, dev);
|
|
|
printf_ATY_D("\r\n");
|
|
|
@@ -394,238 +409,256 @@ uint8_t AD7124_ReadAllReg(struct AD7124_ATY_Cfg* cfg, struct AD7124_ATY_Dev* dev
|
|
|
#endif /* __AD7124_ATY_C */
|
|
|
|
|
|
/************************************ etc *************************************/
|
|
|
-/* init */
|
|
|
-// #include "AD7124_ATY.h"
|
|
|
-// void AD7124_1_NSS_SET(uint8_t level){
|
|
|
-// if(level == __ATY_HL_L)
|
|
|
-// GPIO_SET_L(SPI2_NSS_GPIO_Port, SPI2_NSS_Pin);
|
|
|
-// else if(level == __ATY_HL_H)
|
|
|
-// GPIO_SET_H(SPI2_NSS_GPIO_Port, SPI2_NSS_Pin);
|
|
|
-// }
|
|
|
-// void AD7124_1_EN_SET(uint8_t level){ }
|
|
|
-// void AD7124_1_SYNC_SET(uint8_t level){ }
|
|
|
-// uint8_t AD7124_1_SPI(uint8_t* data_t, uint16_t len, uint8_t rw){
|
|
|
-// if(rw == _ATY_RW_RW)
|
|
|
-// return HAL_SPI_TransmitReceive(&hspi2, (uint8_t*)data_t, (uint8_t*)data_t, len, 1000);
|
|
|
-// return 0;
|
|
|
-// }
|
|
|
-// struct AD7124_ATY_Dev AD7124_ATY_Dev_1 = {
|
|
|
-// .id = 0,
|
|
|
-// .nssSet = AD7124_1_NSS_SET,
|
|
|
-// .enSet = AD7124_1_EN_SET,
|
|
|
-// .syncSet = AD7124_1_SYNC_SET,
|
|
|
-// .spiProcess = AD7124_1_SPI,
|
|
|
-// .delay = HAL_Delay,
|
|
|
-// .lock = __ATY_UNLOCKED,
|
|
|
-// .debugEnable = 0,
|
|
|
-// };
|
|
|
-
|
|
|
-
|
|
|
-/* config template */
|
|
|
-// struct AD7124_ATY_Cfg AD7124_ATY_Cfg_CHIP_T = {
|
|
|
-// .AD7124_ADC_CTRL_REG_t = 0x0580,
|
|
|
-//
|
|
|
-// .AD7124_CFG0_REG_t = 0x09F0,
|
|
|
-//
|
|
|
-// .AD7124_CH0_MAP_REG_t = 0x8211, // IC Temp, int vref
|
|
|
-// };
|
|
|
-// struct AD7124_ATY_Cfg AD7124_ATY_Cfg_NTC10_O1 = {
|
|
|
-// .AD7124_ADC_CTRL_REG_t = 0x0580,
|
|
|
-//
|
|
|
-// .AD7124_CFG1_REG_t = 0x09F0,
|
|
|
-// .AD7124_FILT1_REG_t = 0x0060180,
|
|
|
-// .AD7124_GAIN1_REG_t = 0x5558CC,
|
|
|
-//
|
|
|
-// .AD7124_CH0_MAP_REG_t = 0x918D,
|
|
|
-// };
|
|
|
-// struct AD7124_ATY_Cfg AD7124_ATY_Cfg_RTD4_1 = {
|
|
|
-// .AD7124_ADC_CTRL_REG_t = 0x0480,
|
|
|
-// .AD7124_IO_CTRL1_REG_t = 0x000400,
|
|
|
-// // .AD7124_ERREN_REG_t = 0x06FFFF,
|
|
|
-//
|
|
|
-// .AD7124_CFG0_REG_t = 0x09E4,
|
|
|
-// .AD7124_FILT0_REG_t = 0x0060180,
|
|
|
-// .AD7124_GAIN0_REG_t = 0x5558CC,
|
|
|
-// .AD7124_CH0_MAP_REG_t = 0x9211, //IC Temp
|
|
|
-//
|
|
|
-// .AD7124_CFG1_REG_t = 0x09E4,
|
|
|
-// .AD7124_FILT1_REG_t = 0x0060180,
|
|
|
-// .AD7124_GAIN1_REG_t = 0x05558CC,
|
|
|
-// .AD7124_CH1_MAP_REG_t = 0x9022,
|
|
|
-// };
|
|
|
-// struct AD7124_ATY_Cfg AD7124_ATY_Cfg_NTC1_1 = {
|
|
|
-// .AD7124_ADC_CTRL_REG_t = 0x0480,
|
|
|
-// .AD7124_IO_CTRL1_REG_t = 0x002040,
|
|
|
-//
|
|
|
-// .AD7124_CFG1_REG_t = 0x09E1,
|
|
|
-// .AD7124_FILT1_REG_t = 0x0060180,
|
|
|
-// .AD7124_GAIN1_REG_t = 0x05558CC,
|
|
|
-// // 500uA * 5.11K = 2.5Vref, 1K gain 2 max
|
|
|
-// .AD7124_CH2_MAP_REG_t = 0x90A6,
|
|
|
-// };
|
|
|
-// struct AD7124_ATY_Cfg AD7124_ATY_Cfg_NTC10_1 = {
|
|
|
-// .AD7124_ADC_CTRL_REG_t = 0x0580,
|
|
|
-//
|
|
|
-// .AD7124_CFG1_REG_t = 0x09F0,
|
|
|
-// .AD7124_FILT1_REG_t = 0x0060180,
|
|
|
-// .AD7124_GAIN1_REG_t = 0x5558CC,
|
|
|
-//
|
|
|
-// .AD7124_CH3_MAP_REG_t = 0x918D,
|
|
|
-// .AD7124_CH4_MAP_REG_t = 0x91CF,
|
|
|
-// };
|
|
|
-// struct AD7124_ATY_Cfg AD7124_ATY_Cfg_TC_1 = {
|
|
|
-// .AD7124_ADC_CTRL_REG_t = 0x0580,
|
|
|
-// .AD7124_IO_CTRL2_REG_t = 0x0500,
|
|
|
-//
|
|
|
-// .AD7124_CFG1_REG_t = 0x09F7,
|
|
|
-// .AD7124_FILT1_REG_t = 0x0060180,
|
|
|
-// .AD7124_GAIN1_REG_t = 0x5558CC,
|
|
|
-//
|
|
|
-// .AD7124_CH5_MAP_REG_t = 0x9109,
|
|
|
-// .AD7124_CH6_MAP_REG_t = 0x914B,
|
|
|
-// };
|
|
|
-
|
|
|
-
|
|
|
-/* use */
|
|
|
-// tested 20ms fastest at stm32f103cbt6, spi 18MBit/s, line 50mm
|
|
|
-
|
|
|
-// uint8_t group_AD7124_Data[5] = {0};
|
|
|
-
|
|
|
-// uint8_t adDetectType = 0; // 0: IC temp / user channel, 1: RTD, 2: NTC1K, 34: NTC10K, 56: TC
|
|
|
-// uint8_t adInitFlag = 0;
|
|
|
-
|
|
|
-// uint32_t ad7124Code = 0;
|
|
|
-// uint8_t ad7124End = 0;
|
|
|
-// uint8_t ad7124State = 0;
|
|
|
-
|
|
|
-// #define AD_INIT_MAX_COUNT 8
|
|
|
-// void AD7124_Calc(uint8_t* codeGroup){
|
|
|
-// if((codeGroup[4] & 0x80) != 0){
|
|
|
-// adInitFlag++;
|
|
|
-// if(adInitFlag > AD_INIT_MAX_COUNT){
|
|
|
-// adInitFlag = 0;
|
|
|
-// }
|
|
|
-// return;
|
|
|
-// }
|
|
|
-//
|
|
|
-// if((codeGroup[4] & 0x0F) != adDetectType){
|
|
|
-// adInitFlag++;
|
|
|
-// if(adInitFlag > AD_INIT_MAX_COUNT)
|
|
|
-// adInitFlag = 0;
|
|
|
-// return;
|
|
|
-// }
|
|
|
-//
|
|
|
-// ad7124State = codeGroup[4];
|
|
|
-// ad7124End = codeGroup[0];
|
|
|
-// ad7124Code = (codeGroup[3] + (codeGroup[2] << 8) + (codeGroup[1] << 16));
|
|
|
-//
|
|
|
-// float calcVol = 0, calcRes = 0, fastTempCalc = 0, aboveTempCalc = 0, belowTempCalc = 0;
|
|
|
-// if((codeGroup[4] & 0x0F) == 0){ // IC Temp
|
|
|
-// fastTempCalc = ((float)(ad7124Code - 0x800000) / 13584.0) - 272.5;
|
|
|
-// }
|
|
|
-// if((codeGroup[4] & 0x0F) == 1){ // RTD4
|
|
|
-// calcRes = AD7124_DataToRes(ad7124Code, 24, 5110.0, 16);
|
|
|
-// }
|
|
|
-// if((codeGroup[4] & 0x0F) == 2){ // NTC1K
|
|
|
-// calcRes = AD7124_DataToRes(ad7124Code, 24, 5110.0, 2);
|
|
|
-// }
|
|
|
-// if(((codeGroup[4] & 0x0F) == 3) || ((codeGroup[4] & 0x0F) == 4)){ // NTC10K
|
|
|
-// calcRes = 10.0 * 1000.0 * ((double)((double)(ad7124Code - 0x800000) / (double)(0x1000000 - ad7124Code)));
|
|
|
-// }
|
|
|
-// if(((codeGroup[4] & 0x0F) == 5) || ((codeGroup[4] & 0x0F) == 6)){ // TC
|
|
|
-// calcVol = (((float)ad7124Code - 8388608.0) * 2500.0 / (128.0 * 8388608.0));
|
|
|
-// }
|
|
|
-// }
|
|
|
-
|
|
|
-// void AD7124_Detect(void){
|
|
|
-// static uint8_t lastChannel = 0;
|
|
|
-// if(lastChannel != adDetectType){
|
|
|
-// lastChannel = adDetectType;
|
|
|
-// adInitFlag = 0;
|
|
|
-// }
|
|
|
-// switch(adDetectType){
|
|
|
-// case 0:
|
|
|
-// case 1:
|
|
|
-// if(adInitFlag == 0){
|
|
|
-// adInitFlag = 1;
|
|
|
-// // AD7124_Init(&AD7124_ATY_Cfg_CHIP_T, &AD7124_ATY_Dev_1);
|
|
|
-// AD7124_Init(&AD7124_ATY_Cfg_RTD4_1, &AD7124_ATY_Dev_1);
|
|
|
-// // AD7124_Calibrate(AD7124_CALIBRATE_INT_FULL | AD7124_CALIBRATE_INT_ZERO,
|
|
|
-// // &AD7124_ATY_Cfg_RTD4_1, &AD7124_ATY_Dev_1);
|
|
|
-// }
|
|
|
-// AD7124_ReadData(group_AD7124_Data, &AD7124_ATY_Dev_1);
|
|
|
-// AD7124_Calc(group_AD7124_Data);
|
|
|
-// AD7124_ReadData(group_AD7124_Data, &AD7124_ATY_Dev_1);
|
|
|
-// AD7124_Calc(group_AD7124_Data);
|
|
|
-// break;
|
|
|
-// case 2:
|
|
|
-// if(adInitFlag == 0){
|
|
|
-// adInitFlag = 1;
|
|
|
-// AD7124_Init(&AD7124_ATY_Cfg_NTC1_1, &AD7124_ATY_Dev_1);
|
|
|
-// AD7124_Calibrate(AD7124_CALIBRATE_INT_FULL | AD7124_CALIBRATE_INT_ZERO,
|
|
|
-// &AD7124_ATY_Cfg_NTC1_1, &AD7124_ATY_Dev_1);
|
|
|
-// }
|
|
|
-// AD7124_ReadData(group_AD7124_Data, &AD7124_ATY_Dev_1);
|
|
|
-// AD7124_Calc(group_AD7124_Data);
|
|
|
-// break;
|
|
|
-// case 3:
|
|
|
-// case 4:
|
|
|
-// if(adInitFlag == 0){
|
|
|
-// adInitFlag = 1;
|
|
|
-// AD7124_Init(&AD7124_ATY_Cfg_NTC10_1, &AD7124_ATY_Dev_1);
|
|
|
-// AD7124_Calibrate(AD7124_CALIBRATE_INT_FULL | AD7124_CALIBRATE_INT_ZERO,
|
|
|
-// &AD7124_ATY_Cfg_NTC10_1, &AD7124_ATY_Dev_1);
|
|
|
-// }
|
|
|
-// AD7124_ReadData(group_AD7124_Data, &AD7124_ATY_Dev_1);
|
|
|
-// AD7124_Calc(group_AD7124_Data);
|
|
|
-// AD7124_ReadData(group_AD7124_Data, &AD7124_ATY_Dev_1);
|
|
|
-// AD7124_Calc(group_AD7124_Data);
|
|
|
-// break;
|
|
|
-// case 5:
|
|
|
-// case 6:
|
|
|
-// if(adInitFlag == 0){
|
|
|
-// adInitFlag = 1;
|
|
|
-// AD7124_Init(&AD7124_ATY_Cfg_TC_1, &AD7124_ATY_Dev_1);
|
|
|
-// AD7124_Calibrate(AD7124_CALIBRATE_INT_FULL | AD7124_CALIBRATE_INT_ZERO,
|
|
|
-// &AD7124_ATY_Cfg_TC_1, &AD7124_ATY_Dev_1);
|
|
|
-// }
|
|
|
-// AD7124_ReadData(group_AD7124_Data, &AD7124_ATY_Dev_1);
|
|
|
-// AD7124_Calc(group_AD7124_Data);
|
|
|
-// AD7124_ReadData(group_AD7124_Data, &AD7124_ATY_Dev_1);
|
|
|
-// AD7124_Calc(group_AD7124_Data);
|
|
|
-// break;
|
|
|
-// default:
|
|
|
-// break;
|
|
|
-// }
|
|
|
-// }
|
|
|
-
|
|
|
-/* calc */
|
|
|
-// // IC Temp
|
|
|
-// fastTempCalc = ((float)(ad7124Code - 0x800000) / 13584.0) - 272.5;
|
|
|
-
|
|
|
-// // RTD4
|
|
|
-// calcRes = AD7124_DataToRes(ad7124Code, 24, 5110.0, 16);
|
|
|
-// fastTempCalc = ALGO_Temp_RTD_Res_Fast(calcRes);
|
|
|
-// aboveTempCalc = ALGO_Temp_RTD_Res_Above(calcRes);
|
|
|
-// belowTempCalc = ALGO_Temp_RTD_Res_Below(calcRes);
|
|
|
-
|
|
|
-// // NTC1K
|
|
|
-// calcRes = AD7124_DataToRes(ad7124Code, 24, 5110.0, 2);
|
|
|
-// fastTempCalc = ALGO_ResToKelvinTemp((calcRes / 1000.0), 1.0, 3950);
|
|
|
-// // NTC10K
|
|
|
-// calcVol = (((float)ad7124Code - 8388608.0) * 2500.0 / (1.0 * 8388608.0));
|
|
|
-// calcRes = ((calcVol * 10.0) / (2500.0 - calcVol));
|
|
|
-// fastTempCalc = ALGO_ResToKelvinTemp(calcRes, 10.0, 3380);
|
|
|
-
|
|
|
-// // TC
|
|
|
-// calcVol = (((float)ad7124Code - 8388608.0) * 2500.0 / (128.0 * 8388608.0));
|
|
|
-// float coldTemp = 25.0;
|
|
|
-// float calcVolCold = ALGO_Temp_TC_TempToVol('T', coldTemp);
|
|
|
-// calcVol += calcVolCold;
|
|
|
-// aboveTempCalc = ALGO_Temp_TC_VolToTemp('T', calcVol);
|
|
|
-// belowTempCalc = ALGO_Temp_TC_VolToTemp('T', calcVol);
|
|
|
-// fastTempCalc = aboveTempCalc;
|
|
|
+/* init
|
|
|
+// AD7124 ----------------------------------------------------------------------
|
|
|
+#include "AD7124_ATY.h"
|
|
|
+uint8_t group_AD7124_Data[5] = {0};
|
|
|
+void AD7124_1_NSS_SET(uint8_t level){
|
|
|
+ if(level == __ATY_HL_L)
|
|
|
+ HAL_GPIO_WritePin(SPI2_NSS_GPIO_Port, SPI2_NSS_Pin, GPIO_PIN_RESET);
|
|
|
+ else if(level == __ATY_HL_H)
|
|
|
+ HAL_GPIO_WritePin(SPI2_NSS_GPIO_Port, SPI2_NSS_Pin, GPIO_PIN_SET);
|
|
|
+}
|
|
|
+void AD7124_1_EN_SET(uint8_t level){}
|
|
|
+void AD7124_1_SYNC_SET(uint8_t level){}
|
|
|
+uint8_t AD7124_1_SPI(uint8_t* data_t, uint16_t len){
|
|
|
+ return HAL_SPI_TransmitReceive(&hspi2, (uint8_t*)data_t, (uint8_t*)data_t, len, 1000);
|
|
|
+}
|
|
|
+
|
|
|
+// config template
|
|
|
+struct AD7124_ATY_Cfg AD7124_ATY_Cfg_CHIP_T = {
|
|
|
+ .AD7124_ADC_CTRL_REG_t = 0x0580,
|
|
|
+
|
|
|
+ .AD7124_CFG0_REG_t = 0x09F0,
|
|
|
+
|
|
|
+ .AD7124_CH0_MAP_REG_t = 0x8211, // IC Temp, int vref
|
|
|
+};
|
|
|
+struct AD7124_ATY_Cfg AD7124_ATY_Cfg_NTC10_O1 = {
|
|
|
+ .AD7124_ADC_CTRL_REG_t = 0x0580,
|
|
|
+
|
|
|
+ .AD7124_CFG1_REG_t = 0x09F0,
|
|
|
+ .AD7124_FILT1_REG_t = 0x0060180,
|
|
|
+ .AD7124_GAIN1_REG_t = 0x5558CC,
|
|
|
+
|
|
|
+ .AD7124_CH0_MAP_REG_t = 0x918D,
|
|
|
+};
|
|
|
+
|
|
|
+struct AD7124_ATY_Cfg AD7124_ATY_Cfg_RTD4_1 = {
|
|
|
+ .AD7124_ADC_CTRL_REG_t = 0x0480,
|
|
|
+ .AD7124_IO_CTRL1_REG_t = 0x000400,
|
|
|
+ // .AD7124_ERREN_REG_t = 0x06FFFF,
|
|
|
+
|
|
|
+ .AD7124_CFG0_REG_t = 0x09E4,
|
|
|
+ .AD7124_FILT0_REG_t = 0x0060180,
|
|
|
+ .AD7124_GAIN0_REG_t = 0x5558CC,
|
|
|
+ .AD7124_CH0_MAP_REG_t = 0x9211, //IC Temp
|
|
|
+
|
|
|
+ .AD7124_CFG1_REG_t = 0x09E4,
|
|
|
+ .AD7124_FILT1_REG_t = 0x0060180,
|
|
|
+ .AD7124_GAIN1_REG_t = 0x05558CC,
|
|
|
+ .AD7124_CH1_MAP_REG_t = 0x9022,
|
|
|
+};
|
|
|
+struct AD7124_ATY_Cfg AD7124_ATY_Cfg_NTC1_1 = {
|
|
|
+ .AD7124_ADC_CTRL_REG_t = 0x0480,
|
|
|
+ .AD7124_IO_CTRL1_REG_t = 0x002040,
|
|
|
+
|
|
|
+ .AD7124_CFG1_REG_t = 0x09E1,
|
|
|
+ .AD7124_FILT1_REG_t = 0x0060180,
|
|
|
+ .AD7124_GAIN1_REG_t = 0x05558CC,
|
|
|
+ // 500uA * 5.11K = 2.5Vref, 1K gain 2 max
|
|
|
+ .AD7124_CH2_MAP_REG_t = 0x90A6,
|
|
|
+};
|
|
|
+struct AD7124_ATY_Cfg AD7124_ATY_Cfg_NTC10_1 = {
|
|
|
+ .AD7124_ADC_CTRL_REG_t = 0x0580,
|
|
|
+
|
|
|
+ .AD7124_CFG1_REG_t = 0x09F0,
|
|
|
+ .AD7124_FILT1_REG_t = 0x0060180,
|
|
|
+ .AD7124_GAIN1_REG_t = 0x5558CC,
|
|
|
+
|
|
|
+ .AD7124_CH3_MAP_REG_t = 0x918D,
|
|
|
+ .AD7124_CH4_MAP_REG_t = 0x91CF,
|
|
|
+};
|
|
|
+struct AD7124_ATY_Cfg AD7124_ATY_Cfg_TC_1 = {
|
|
|
+ .AD7124_ADC_CTRL_REG_t = 0x0580,
|
|
|
+ .AD7124_IO_CTRL2_REG_t = 0x0500,
|
|
|
+
|
|
|
+ .AD7124_CFG1_REG_t = 0x09F7,
|
|
|
+ .AD7124_FILT1_REG_t = 0x0060180,
|
|
|
+ .AD7124_GAIN1_REG_t = 0x5558CC,
|
|
|
+
|
|
|
+ .AD7124_CH5_MAP_REG_t = 0x9109,
|
|
|
+ .AD7124_CH6_MAP_REG_t = 0x914B,
|
|
|
+};
|
|
|
+
|
|
|
+struct AD7124_ATY_Dev AD7124_ATY_Dev_1 = {
|
|
|
+ .enSet = AD7124_1_EN_SET,
|
|
|
+ .syncSet = AD7124_1_SYNC_SET,
|
|
|
+ .nssSet = AD7124_1_NSS_SET,
|
|
|
+ .spiProcess = AD7124_1_SPI,
|
|
|
+ .initFlag = 0,
|
|
|
+
|
|
|
+ .addr = 0,
|
|
|
+ .id = 0,
|
|
|
+ .data = group_AD7124_Data,
|
|
|
+ // .cfg = &AD7124_ATY_Cfg_NTC10_O1,
|
|
|
+ .cfg = &AD7124_ATY_Cfg_CHIP_T,
|
|
|
+
|
|
|
+ .delay = HAL_Delay,
|
|
|
+
|
|
|
+ .lock = __ATY_UNLOCKED
|
|
|
+};
|
|
|
+*/
|
|
|
+
|
|
|
+/* use
|
|
|
+// tested 18ms fastest at stm32f103cbt6 72MHz, spi 18MBit/s, line 50mm, signal channel IC T
|
|
|
+#define AD_INIT_MAX_COUNT 8
|
|
|
+uint8_t adDetectType = 0; // 0: IC Temp / user channel, 1: RTD, 2: NTC1K, 34: NTC10K, 56: TC
|
|
|
+uint32_t ad7124Code = 0;
|
|
|
+
|
|
|
+void AD7124_Calc(uint8_t* codeGroup){
|
|
|
+ if((codeGroup[4] & 0x80) != 0){
|
|
|
+ AD7124_ATY_Dev_1.initFlag++;
|
|
|
+ if(AD7124_ATY_Dev_1.initFlag > AD_INIT_MAX_COUNT){
|
|
|
+ AD7124_ATY_Dev_1.initFlag = 0;
|
|
|
+ }
|
|
|
+ return;
|
|
|
+ }
|
|
|
+
|
|
|
+ if((codeGroup[4] & 0x0F) != adDetectType){
|
|
|
+ AD7124_ATY_Dev_1.initFlag++;
|
|
|
+ if(AD7124_ATY_Dev_1.initFlag > AD_INIT_MAX_COUNT)
|
|
|
+ AD7124_ATY_Dev_1.initFlag = 0;
|
|
|
+ return;
|
|
|
+ }
|
|
|
+
|
|
|
+ ad7124Code = (codeGroup[3] + (codeGroup[2] << 8) + (codeGroup[1] << 16));
|
|
|
|
|
|
+ printf_ATY("\r\nChip: %f", (((float)(ad7124Code - 0x800000) / 13584.0) - 272.5));
|
|
|
+
|
|
|
+ // Type Calc
|
|
|
+ float calcVol = 0, calcRes = 0, fastTempCalc = 0, aboveTempCalc = 0, belowTempCalc = 0;
|
|
|
+ if((codeGroup[4] & 0x0F) == 0){ // IC Temp
|
|
|
+ fastTempCalc = ((float)(ad7124Code - 0x800000) / 13584.0) - 272.5;
|
|
|
+ }
|
|
|
+ if((codeGroup[4] & 0x0F) == 1){ // RTD4
|
|
|
+ calcRes = AD7124_DataToRes(ad7124Code, 24, 5110.0, 16);
|
|
|
+ }
|
|
|
+ if((codeGroup[4] & 0x0F) == 2){ // NTC1K
|
|
|
+ calcRes = AD7124_DataToRes(ad7124Code, 24, 5110.0, 2);
|
|
|
+ }
|
|
|
+ if(((codeGroup[4] & 0x0F) == 3) || ((codeGroup[4] & 0x0F) == 4)){ // NTC10K
|
|
|
+ calcRes = 10.0 * 1000.0 * ((double)((double)(ad7124Code - 0x800000) / (double)(0x1000000 - ad7124Code)));
|
|
|
+ }
|
|
|
+ if(((codeGroup[4] & 0x0F) == 5) || ((codeGroup[4] & 0x0F) == 6)){ // TC
|
|
|
+ calcVol = (((float)ad7124Code - 8388608.0) * 2500.0 / (128.0 * 8388608.0));
|
|
|
+ }
|
|
|
+
|
|
|
+ // Type Table, put table out of function!!
|
|
|
+ const uint16_t RT_table_N30toP50_1_T_size = 81;
|
|
|
+ const double RT_table_N30toP50_1_T[81] = {-30, -29, -28, -27, -26, -25, -24, -23, -22, -21, -20, -19, -18, -17, -16, -15, -14, -13, -12, -11, -10, -9, -8, -7, -6, -5, -4, -3, -2, -1, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50};
|
|
|
+ const double RT_table_PT1000_N30toP50_1_R[81] = {882.21656767, 886.1604620248771, 890.1030863723519, 894.0444460833969, 897.984546428592, 901.9233925781249, 905.8609896017921, 909.797342468997, 913.7324560487519, 917.666335109677, 921.5989843200001, 925.530408247557, 929.460611359792, 933.389598023757, 937.317372506112, 941.243938973125, 945.1693014906721, 949.0934640242369, 953.0164304389119, 956.938204499397, 960.85878987, 964.7781901146369, 968.696408696832, 972.613448979717, 976.529314226032, 980.444007598125, 984.3575321579519, 988.2698908670769, 992.1810865866721, 996.091122077517, 1000, 1003.9077225, 1007.81429, 1011.7197025, 1015.6239599999999, 1019.5270625000002, 1023.4290100000001, 1027.3298025, 1031.2294399999998, 1035.1279225, 1039.02525, 1042.9214224999998, 1046.81644, 1050.7103025, 1054.60301, 1058.4945625000003, 1062.38496, 1066.2742025, 1070.16229, 1074.0492225, 1077.935, 1081.8196225, 1085.70309, 1089.5854024999999, 1093.46656, 1097.3465625000001, 1101.22541, 1105.1031025, 1108.97964, 1112.8550225, 1116.7292499999999, 1120.6023225, 1124.47424, 1128.3450025000002, 1132.2146100000002, 1136.0830625, 1139.95036, 1143.8165025, 1147.68149, 1151.5453224999999, 1155.408, 1159.2695224999998, 1163.12989, 1166.9891025000002, 1170.84716, 1174.7040625, 1178.5598100000002, 1182.4144025, 1186.26784, 1190.1201225, 1193.97125};
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+ const double RT_table_NTC10K_B3950_N30toP50_1_R[81] = {200203.9024466842, 187316.35371436414, 175353.56517945265, 164242.815037761, 153917.57353446394, 144316.93726809666, 135385.11855020453, 127070.98414555467, 119327.63833441163, 112112.04578468086, 105384.690206038, 99109.26518793346, 93252.3940049376, 87783.37551199133, 82673.95355365716, 77898.10757980836, 73431.86239916032, 69253.11521500889, 65341.47827746307, 61678.13565594302, 58245.71278707882, 55028.15758840015, 52010.63204917008, 49179.41331794596, 46521.80340337541, 44026.046691571566, 41681.25456127495, 39477.33644786429, 37404.936769989145, 35455.37718893085, 33620.60372143574, 31893.138272305434, 30266.034194017953, 28732.835517560583, 27287.53953191174, 25924.56241959352, 24638.70768276219, 23425.137118719744, 22279.344125776763, 21197.12914032421, 20174.57702398485, 19208.036236013788, 18294.09964087108, 17429.586814247774, 16611.527722935953, 15837.147664908136, 15103.853365929419, 14409.220138062792, 13750.980013633698, 13127.010775676536, 12535.32581266281, 11974.064731474306, 11441.484668193882, 10935.952241391826, 10455.936097237052, 10000, 9566.796425378521, 9155.060617602236, 8763.605074487228, 8391.314427550227, 8037.140686973136, 7700.09882366077, 7379.2626628761145, 7073.761065987096, 6782.774378735532, 6505.531126156567, 6241.304935849771, 5989.411672745506, 5749.206769831047, 5520.082740513648, 5301.466859409668, 5092.818999369683, 4893.62961348718, 4703.417851699504, 4521.7298023814565, 4348.136850059472, 4182.234141043995, 4023.6391493935307, 3871.990336190894, 3726.945895634597, 3588.1825819290834};
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|
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+ const double RT_table_NTC10K_B3380_N30toP50_1_R[81] = {129916.73842576398, 122726.45506217859, 115987.98389609528, 109669.80710548842, 103742.81092588141, 98180.08736222527, 92956.75343550005, 88049.78631286524, 83437.87283482423, 79101.27210022854, 75021.689901878, 71182.16392373295, 67566.95871677202, 64161.46956567978, 60952.13444397613, 57926.35333195929, 55072.41424084727, 52379.42534858893, 49837.25270871057, 47436.46304390781, 45168.27118147633, 43024.49172859917, 40997.49462244794, 39080.16422340271, 37265.86164983361, 35548.39008012747, 33921.96277228722, 32381.173573736873, 30920.9697141643, 29536.62669253702, 28223.725086022154, 26978.129123593826, 25795.96688077618, 24673.61196437721, 23607.66656734277, 22594.945784110834, 21632.463086167136, 20717.41686598908, 19847.177965288593, 19019.278110503867, 18231.399184902846, 17481.363272511575, 16767.123414418118, 16086.755022872807, 15438.44790305672, 14820.498836453826, 14231.304683479702, 13669.355966418227, 13133.230896827301, 12621.589814422336, 12133.170007053395, 11666.78088378108, 11221.299475246835, 10795.666237541593, 10388.881137620136, 10000, 9628.131096037672, 9272.431958502, 8932.106405476528, 8606.401758829414, 8294.606243598528, 7996.046555661133, 7710.085585997876, 7436.120290726329, 7173.579696877923, 6921.923034627457, 6680.637987362497, 6449.239051606348, 6227.265999385221, 6014.2824361639205, 5809.8744479667575, 5613.649331755301, 5425.234403555528, 5244.275879215621, 5070.437823035709, 4903.401159843523, 4742.862746398391, 4588.534498291319, 4440.142568773257, 4297.426576188887, 4160.138876920097};
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|
|
+ if(ntcType == 0){
|
|
|
+ fastTempCalc = ALGO_RT_Table_R2T(calcRes * 1.0,
|
|
|
+ RT_table_N30toP50_1_T,
|
|
|
+ RT_table_Custom3950_N30toP50_1_R,
|
|
|
+ RT_table_N30toP50_1_T_size);
|
|
|
+ }
|
|
|
+ else if(ntcType == 1){
|
|
|
+ fastTempCalc = ALGO_RT_Table_R2T(calcRes * 1.0,
|
|
|
+ RT_table_N30toP50_1_T,
|
|
|
+ RT_table_NTC10K_B3380_N30toP50_1_R,
|
|
|
+ RT_table_N30toP50_1_T_size);
|
|
|
+ }
|
|
|
+ else if(ntcType == 2){
|
|
|
+ fastTempCalc = ALGO_RT_Table_R2T(calcRes * 1.0,
|
|
|
+ RT_table_N30toP50_1_T,
|
|
|
+ RT_table_NTC10K_B3950_N30toP50_1_R,
|
|
|
+ RT_table_N30toP50_1_T_size);
|
|
|
+ }
|
|
|
+ // offset
|
|
|
+ fastTempCalc = (fastTempCalc * 1000.0) + 180.0;
|
|
|
+}
|
|
|
+
|
|
|
+void AD7124_Detect(void){
|
|
|
+ static uint8_t lastChannel = 0;
|
|
|
+ if(lastChannel != adDetectType){
|
|
|
+ lastChannel = adDetectType;
|
|
|
+ AD7124_ATY_Dev_1.initFlag++;
|
|
|
+ if(AD7124_ATY_Dev_1.initFlag > AD_INIT_MAX_COUNT)
|
|
|
+ AD7124_ATY_Dev_1.initFlag = 0;
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|
|
+ return;
|
|
|
+ }
|
|
|
+ switch(adDetectType){
|
|
|
+ case 0:
|
|
|
+ case 1:
|
|
|
+ // AD7124_Calibrate(AD7124_CALIBRATE_INT_FULL | AD7124_CALIBRATE_INT_ZERO,
|
|
|
+ // &AD7124_ATY_Cfg_RTD4_1, &AD7124_ATY_Dev_1);
|
|
|
+ AD7124_ReadData(group_AD7124_Data, &AD7124_ATY_Dev_1);
|
|
|
+ AD7124_Calc(group_AD7124_Data);
|
|
|
+ AD7124_ReadData(group_AD7124_Data, &AD7124_ATY_Dev_1);
|
|
|
+ AD7124_Calc(group_AD7124_Data);
|
|
|
+ break;
|
|
|
+ case 2:
|
|
|
+ AD7124_Calibrate(AD7124_CALIBRATE_INT_FULL | AD7124_CALIBRATE_INT_ZERO,
|
|
|
+ &AD7124_ATY_Cfg_NTC1_1, &AD7124_ATY_Dev_1);
|
|
|
+ AD7124_ReadData(group_AD7124_Data, &AD7124_ATY_Dev_1);
|
|
|
+ AD7124_Calc(group_AD7124_Data);
|
|
|
+ break;
|
|
|
+ case 3:
|
|
|
+ case 4:
|
|
|
+ AD7124_Calibrate(AD7124_CALIBRATE_INT_FULL | AD7124_CALIBRATE_INT_ZERO,
|
|
|
+ &AD7124_ATY_Cfg_NTC10_1, &AD7124_ATY_Dev_1);
|
|
|
+ AD7124_ReadData(group_AD7124_Data, &AD7124_ATY_Dev_1);
|
|
|
+ AD7124_Calc(group_AD7124_Data);
|
|
|
+ AD7124_ReadData(group_AD7124_Data, &AD7124_ATY_Dev_1);
|
|
|
+ AD7124_Calc(group_AD7124_Data);
|
|
|
+ break;
|
|
|
+ case 5:
|
|
|
+ case 6:
|
|
|
+ AD7124_Calibrate(AD7124_CALIBRATE_INT_FULL | AD7124_CALIBRATE_INT_ZERO,
|
|
|
+ &AD7124_ATY_Cfg_TC_1, &AD7124_ATY_Dev_1);
|
|
|
+ AD7124_ReadData(group_AD7124_Data, &AD7124_ATY_Dev_1);
|
|
|
+ AD7124_Calc(group_AD7124_Data);
|
|
|
+ AD7124_ReadData(group_AD7124_Data, &AD7124_ATY_Dev_1);
|
|
|
+ AD7124_Calc(group_AD7124_Data);
|
|
|
+ break;
|
|
|
+ default:
|
|
|
+ break;
|
|
|
+ }
|
|
|
+}
|
|
|
+*/
|
|
|
+
|
|
|
+
|
|
|
+/* calc
|
|
|
+// IC Temp
|
|
|
+fastTempCalc = ((float)(ad7124Code - 0x800000) / 13584.0) - 272.5;
|
|
|
+
|
|
|
+// RTD4
|
|
|
+calcRes = AD7124_DataToRes(ad7124Code, 24, 5110.0, 16);
|
|
|
+fastTempCalc = ALGO_Temp_RTD_Res_Fast(calcRes);
|
|
|
+aboveTempCalc = ALGO_Temp_RTD_Res_Above(calcRes);
|
|
|
+belowTempCalc = ALGO_Temp_RTD_Res_Below(calcRes);
|
|
|
+
|
|
|
+// NTC1K
|
|
|
+calcRes = AD7124_DataToRes(ad7124Code, 24, 5110.0, 2);
|
|
|
+fastTempCalc = ALGO_ResToKelvinTemp((calcRes / 1000.0), 1.0, 3950);
|
|
|
+
|
|
|
+// NTC10K
|
|
|
+calcVol = (((float)ad7124Code - 8388608.0) * 2500.0 / (1.0 * 8388608.0));
|
|
|
+calcRes = ((calcVol * 10.0) / (2500.0 - calcVol));
|
|
|
+fastTempCalc = ALGO_ResToKelvinTemp(calcRes, 10.0, 3380);
|
|
|
+
|
|
|
+// TC
|
|
|
+calcVol = (((float)ad7124Code - 8388608.0) * 2500.0 / (128.0 * 8388608.0));
|
|
|
+float coldTemp = 25.0;
|
|
|
+float calcVolCold = ALGO_Temp_TC_TempToVol('T', coldTemp);
|
|
|
+calcVol += calcVolCold;
|
|
|
+aboveTempCalc = ALGO_Temp_TC_VolToTemp('T', calcVol);
|
|
|
+belowTempCalc = ALGO_Temp_TC_VolToTemp('T', calcVol);
|
|
|
+fastTempCalc = aboveTempCalc;
|
|
|
+*/
|
|
|
|
|
|
/******************************************************************************/
|
|
|
|