ATY_LIB/HW_SPI_ATY.c

/**
* @file HW_SPI_ATY.c
*
* @param Project DEVICE_GENERAL_ATY_LIB
*
* @author ATY
*
* @copyright
*       - Copyright 2017 - 2025 MZ-ATY
*       - This code follows:
*           - MZ-ATY Various Contents Joint Statement -
*               <a href="https://mengze.top/MZ-ATY_VCJS">
*                        https://mengze.top/MZ-ATY_VCJS</a>
*           - CC 4.0 BY-NC-SA -
*               <a href="https://creativecommons.org/licenses/by-nc-sa/4.0/">
*                        https://creativecommons.org/licenses/by-nc-sa/4.0/</a>
*       - Your use will be deemed to have accepted the terms of this statement.
*
* @brief Familiar functions of SPI for all embedded device
*
* @version
*       - 1_01_221028 > ATY
*           -# Preliminary version, first Release
*       - 1_01_240111 > ATY
*           -# add multy addr and channel
*           -# add lock
*           -Undone: in soft
********************************************************************************
*/

#ifndef __HW_SPI_ATY_C
#define __HW_SPI_ATY_C

#include "HW_SPI_ATY.h"

/******************************* For user *************************************/

/******************************************************************************/

/**
 * @brief
 *
 * @param   data_t
 * @param   len
 * @param   dev
 * @return  uint8_t
 */
uint8_t SPI_Write(uint8_t* data_t, uint16_t len, struct HW_SPI_ATY_Dev* dev)
{
    if(dev->hardwareEnable == 1){
        uint8_t errCode = 0;
        __ATY_LOCK(dev);
        errCode = dev->spiProcess(data_t, len, _ATY_RW_W);
        __ATY_UNLOCK(dev);
        return errCode;
    }
    else{ __ATY_UNLOCK(dev); return 1; }
}

/**
 * @brief
 *
 * @param   data_t
 * @param   len
 * @param   dev
 * @return  uint8_t
 */
uint8_t SPI_Read(uint8_t* data_t, uint16_t len, struct HW_SPI_ATY_Dev* dev)
{
    if(dev->hardwareEnable == 1){
        uint8_t errCode = 0;
        __ATY_LOCK(dev);
        errCode = dev->spiProcess(data_t, len, _ATY_RW_R);
        __ATY_UNLOCK(dev);
        return errCode;
    }
    else{ __ATY_UNLOCK(dev); return 1; }
}

/**
 * @brief
 *
 * @param   data_t
 * @param   len
 * @param   dev
 * @return  uint8_t
 */
uint8_t SPI_ReadWrite(uint8_t* data_t, uint16_t len, struct HW_SPI_ATY_Dev* dev)
{
    if(dev->hardwareEnable == 1){
        uint8_t errCode = 0;
        __ATY_LOCK(dev);
        errCode = dev->spiProcess(data_t, len, _ATY_RW_RW);
        __ATY_UNLOCK(dev);
        return errCode;
    }
    else{ __ATY_UNLOCK(dev); return 1; }
}

#endif /* __HW_SPI_ATY_C */

/************************************ etc *************************************/
/* init */
// // STM32 HAL
// uint8_t SPI_1(uint8_t* data_t, uint8_t len, uint8_t rw){
//     if(rw == _ATY_RW_W)
//         return HAL_SPI_Transmit(&hspi2, (uint8_t*)data_t, len, 1000);
//     else if(rw == _ATY_RW_R)
//         return HAL_SPI_Receive(&hspi2, (uint8_t*)data_t, len, 1000);
//     else if(rw == _ATY_RW_RW)
//         return HAL_SPI_TransmitReceive(&hspi2, (uint8_t*)data_t, (uint8_t*)data_t, len, 1000);
//     return 0;
// }

// // 51 // todo: not tested
// uint8_t SPI_1(uint8_t* data_t, uint8_t len, uint8_t rw){
//     if(rw == _ATY_RW_W){
//         uint8_t i = 0;
//         uint16_t errCount = 1000;
//         SPCTL = 0xD4;
//         for(i = 0; i < len; i++)
//         {
//             SPSTAT |= 0xC0;
//             SPDAT = data_t[i];
//             while(((SPSTAT & 0x80) != 0x80) && errCount) errCount--;
//             if(errCount == 0) return 1; else errCount = 1000;
//         }
//         return 0;
//     }
//     else if(rw == _ATY_RW_R){
//         uint8_t i = 0;
//         uint16_t errCode = 1000;
//         SPCTL = 0xD4;
//         for(i = 0; i < len; i++)
//         {
//             SPSTAT |= 0xC0;
//             SPDAT = 0xFF;
//             while(((SPSTAT & 0x80) != 0x80) && errCode) errCode--;
//             if(errCount == 0) return 1; else errCount = 1000;
//             data_t[i] = SPDAT;
//         }
//         return 0;
//     }

//     else if(rw == _ATY_RW_RW){
//         uint8_t i = 0;
//         uint16_t errCount = 1000;
//         SPCTL = 0xD4;

//         SPSTAT |= 0xC0;
//         SPDAT = data_t[0];
//         while(((SPSTAT & 0x80) != 0x80) && errCount) errCount--;
//         if(errCount == 0) return 1; else errCount = 1000;

//         SPCTL = 0xD4;
//         for(i = 0; i < len; i++)
//         {
//             SPSTAT |= 0xC0;
//             SPDAT = 0xFF;
//             while(((SPSTAT & 0x80) != 0x80) && errCount) errCount--;
//             if(errCount == 0) return 1; else errCount = 1000;
//             data_t[i] = SPDAT;
//         }

//         return 0;
//     }
//     return 0;
// }

// // ESP8266_RTOS // todo: not tested
// #include <stdio.h>
// #include "freertos/FreeRTOS.h"
// #include "freertos/task.h"
// #include "freertos/queue.h"
// #include "esp8266/gpio_struct.h"
// #include "esp8266/spi_struct.h"
// #include "esp_system.h"
// #include "esp_log.h"
// #include "esp_libc.h"
// #include "driver/gpio.h"
// #include "driver/spi.h"

// static const char* TAG = "user_spi";

// esp_err_t esp8266_spi_init(void)
// {
//     ESP_LOGI(TAG, "init spi");
//     spi_config_t spi_config;
//     // Load default interface parameters
//     // CS_EN:1, MISO_EN:1, MOSI_EN:1, BYTE_TX_ORDER:1, BYTE_TX_ORDER:1, BIT_RX_ORDER:0, BIT_TX_ORDER:0, CPHA:0, CPOL:0
//     spi_config.interface.val = SPI_DEFAULT_INTERFACE;

//     // Load default interrupt enable
//     // TRANS_DONE: true, WRITE_STATUS: false, READ_STATUS: false, WRITE_BUFFER: false, READ_BUFFER: false
//     spi_config.intr_enable.val = SPI_MASTER_DEFAULT_INTR_ENABLE;

//     spi_config.interface.cs_en = 0;
//     spi_config.interface.mosi_en = 1;
//     spi_config.interface.miso_en = 1;

//     // Set SPI to master mode
//     // ESP8266 Only support half-duplex
//     spi_config.mode = SPI_MASTER_MODE;
//     // Set the SPI clock frequency division factor
//     spi_config.clk_div = SPI_2MHz_DIV;
//     spi_config.event_cb = NULL;
//     return spi_init(HSPI_HOST, &spi_config);
// }

// /**
//  * @brief
//  * @note    use [ESP8266_RTOS_SDK](https://github.com/espressif/ESP8266_RTOS_SDK/)
//  */
// // esp_err_t SPI_Write(uint8_t* data_t, uint16_t len)
// uint8_t SPI_Write(uint8_t* data_t, uint16_t len)
// {
//     spi_trans_t trans = {0};
//     trans.mosi = data;
//     trans.bits.mosi = len * 8;
//     return spi_trans(HSPI_HOST, &trans);
// }

// uint8_t SPI_Read(uint8_t* data_t, uint16_t len)
// {
//     spi_trans_t trans;
//     memset(&trans, 0x0, sizeof(trans));
//     trans.bits.val = 0;
//     trans.miso = data_t;
//     trans.bits.miso = len * 8;
//     if(spi_trans(HSPI_HOST, &trans))
//         return 0;
//     return 1;
// }


// void SPI_Delay(uint8_t t){ }

// struct HW_SPI_ATY_Dev HW_SPI_ATY_Dev_1 = {
//     .hardwareEnable = 1,
//     .spiProcess = SPI_1,
//     .delay = SPI_Delay,
//     .lock = _ATY_UNLOCKED,
//     .debugEnable = 0,
//     .LOG = printf
// };

/* use */
// SPI_Write(data_t, len, &HW_SPI_ATY_Dev_1);
// SPI_Read(data_t, len, &HW_SPI_ATY_Dev_1);
// SPI_ReadWrite(data_t, len, &HW_SPI_ATY_Dev_1);

/******************************************************************************/

/******************************** End Of File *********************************/