fw_pwm.h 22 KB

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  1. // Copyright 2021 IOsetting <iosetting(at)outlook.com>
  2. //
  3. // Licensed under the Apache License, Version 2.0 (the "License");
  4. // you may not use this file except in compliance with the License.
  5. // You may obtain a copy of the License at
  6. //
  7. // http://www.apache.org/licenses/LICENSE-2.0
  8. //
  9. // Unless required by applicable law or agreed to in writing, software
  10. // distributed under the License is distributed on an "AS IS" BASIS,
  11. // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  12. // See the License for the specific language governing permissions and
  13. // limitations under the License.
  14. #ifndef ___FW_PWM_H___
  15. #define ___FW_PWM_H___
  16. #include "fw_conf.h"
  17. #include "fw_types.h"
  18. typedef enum
  19. {
  20. PWM_Pin_1 = B00000001,
  21. PWM_Pin_1N = B00000010,
  22. PWM_Pin_2 = B00000100,
  23. PWM_Pin_2N = B00001000,
  24. PWM_Pin_3 = B00010000,
  25. PWM_Pin_3N = B00100000,
  26. PWM_Pin_4 = B01000000,
  27. PWM_Pin_4N = B10000000,
  28. PWMA_Pin_All = B11111111,
  29. PWMB_Pin_All = B01010101,
  30. } PWM_Pin_t;
  31. /**
  32. * Trigger mode
  33. * Side Mode:
  34. * Depends on DIR
  35. * Center Mode: counter increasing then decreasing
  36. * CenterDown: trigger interrupt when meet target in decreasing
  37. * CenterUp: trigger interrupt when meet target in increasing
  38. * CenterBoth: trigger interrupt when meet target in both
  39. */
  40. typedef enum
  41. {
  42. PWM_EdgeAlignment_Side = 0x00,
  43. PWM_EdgeAlignment_CenterDown = 0x01,
  44. PWM_EdgeAlignment_CenterUp = 0x10,
  45. PWM_EdgeAlignment_CenterBoth = 0x11,
  46. } PWM_EdgeAlignment_t;
  47. typedef enum
  48. {
  49. PWM_CounterDirection_Up = 0x00,
  50. PWM_CounterDirection_Down = 0x01,
  51. } PWM_CounterDirection_t;
  52. /**
  53. * Comparasion Output Mode: PWMx_CCRx vs PWMx_CNT => OCxREF
  54. */
  55. typedef enum
  56. {
  57. PWM_OutputMode_NoAction = 0x00, // Fixed
  58. PWM_OutputMode_TriggerHigh = 0x01, // OCxREF=1 when PWMA_CCR1=PWMA_CNT
  59. PWM_OutputMode_TriggerLow = 0x02, // OCxREF=0 when PWMA_CCR1=PWMA_CNT
  60. PWM_OutputMode_TriggerToggle = 0x03, // Toggle OCxREF when PWMA_CCR1=PWMA_CNT
  61. PWM_OutputMode_AlwaysLow = 0x04, // OCxREF always low
  62. PWM_OutputMode_AlwaysHigh = 0x05, // OCxREF always high
  63. PWM_OutputMode_PWM_HighIfLess = 0x06, // OCxREF=1 when PWMA_CNT<PWMA_CCR1, in both counting direction
  64. PWM_OutputMode_PWM_LowIfLess = 0x07, // OCxREF=0 when PWMA_CNT<PWMA_CCR1, in both counting direction
  65. } PWM_OutputMode_t;
  66. /**************************************************************************** /
  67. * PWMA
  68. */
  69. /**
  70. * PWM clock prescaler and auto-reload period
  71. *
  72. * side alignment:
  73. * Fpwm = SYSCLK / (PWMx_PSCR + 1) / (PWMx_ARR + 1)
  74. * central alignment:
  75. * Fpwm = SYSCLK / (PWMx_PSCR + 1) / PWMx_ARR / 2
  76. */
  77. #define PWMA_SetPrescaler(__16BIT_VAL__) do { \
  78. SFRX_ON(); \
  79. (PWMA_PSCRH = ((__16BIT_VAL__) >> 8)); \
  80. (PWMA_PSCRL = ((__16BIT_VAL__) & 0xFF)); \
  81. SFRX_OFF(); \
  82. }while(0)
  83. #define PWMA_SetPeriod(__16BIT_VAL__) do { \
  84. SFRX_ON(); \
  85. (PWMA_ARRH = ((__16BIT_VAL__) >> 8)); \
  86. (PWMA_ARRL = ((__16BIT_VAL__) & 0xFF)); \
  87. SFRX_OFF(); \
  88. }while(0)
  89. // PWMA all pins input/output OFF/ON
  90. #define PWMA_SetOverallState(__STATE__) SFRX_ASSIGN(PWMA_BKR, 7, (__STATE__))
  91. // PWMA Pins Output OFF/ON
  92. #define PWMA_SetPinOutputState(__PINS__, __STATE__) do { \
  93. SFRX_ON(); \
  94. PWMA_ENO = PWMA_ENO & ~(__PINS__) | (((__STATE__) & 0x01)? (__PINS__) : 0x00); \
  95. SFRX_OFF(); \
  96. } while(0)
  97. // Enable/Disable PWMB_BKR Control on Pins
  98. #define PWMA_SetPinBrakeControl(__PINS__, __STATE__) do { \
  99. SFRX_ON(); \
  100. PWMA_IOAUX = PWMA_IOAUX & ~(__PINS__) | (((__STATE__) & 0x01)? (__PINS__) : 0x00); \
  101. SFRX_OFF(); \
  102. } while(0)
  103. /**
  104. * 0: New period will be written to [PWMA_ARRH,PWMA_ARRL] and take effect immediately
  105. * 1: New period will be written to shadow register and loaded to [PWMA_ARRH,PWMA_ARRL] on next update event
  106. */
  107. #define PWMA_SetAutoReloadPreload(__STATE__) SFRX_ASSIGN(PWMA_CR1, 7, (__STATE__))
  108. /**
  109. * Turn off counter (call PWMA_SetCounterState()) before changing to different alignment
  110. */
  111. #define PWMA_SetEdgeAlignment(__ALIGN__) do{ \
  112. SFRX_ON();(PWMA_CR1 = PWMA_CR1 & ~(0x03 << 5) | ((__ALIGN__) << 5));SFRX_OFF(); \
  113. }while(0)
  114. /**
  115. * 0: count from 0 to [PWMA_ARRH,PWMA_ARRL], then send an event and restart from 0
  116. * 1: count from [PWMA_ARRH,PWMA_ARRL] to 0, then send an event and restart from [PWMA_ARRH,PWMA_ARRL]
  117. */
  118. #define PWMA_SetCounterDirection(__DIR__) SFRX_ASSIGN(PWMA_CR1, 4, (__DIR__))
  119. /**
  120. * 0: counter continues when update event occurs
  121. * 1: counter stops(reset CEN) when update event occurs
  122. */
  123. #define PWMA_SetCounterOnePulse(__STATE__) SFRX_ASSIGN(PWMA_CR1, 3, (__STATE__))
  124. /**
  125. * Work only when update events are enabled
  126. * 0: An interrupt will be triggered by these events: counter overflow(upwards or downwards), soft set UG, timer/controller updates
  127. * 1: An interrupt will be triggered(and set UIF=1) by counter overflow(upwards or downwards)
  128. */
  129. #define PWMA_SetUpdateEventSource(__STATE__) SFRX_ASSIGN(PWMA_CR1, 2, (__STATE__))
  130. /**
  131. * 0:enable update events, 1:disable update events
  132. */
  133. #define PWMA_SetNonUpdateEvent(__STATE__) SFRX_ASSIGN(PWMA_CR1, 1, (__STATE__))
  134. /**
  135. * 0:stop counter, 1:start counter
  136. */
  137. #define PWMA_SetCounterState(__STATE__) SFRX_ASSIGN(PWMA_CR1, 0, (__STATE__))
  138. /**
  139. * PWMA.1 - PWMA.4 io polar and on/off state
  140. */
  141. #define PWMA_PWM1_SetPortState(__STATE__) SFRX_ASSIGN(PWMA_CCER1, 0, (__STATE__))
  142. #define PWMA_PWM1_SetPortPolar(__POLAR__) SFRX_ASSIGN(PWMA_CCER1, 1, (__POLAR__))
  143. #define PWMA_PWM1N_SetPortState(__STATE__) SFRX_ASSIGN(PWMA_CCER1, 2, (__STATE__))
  144. #define PWMA_PWM1N_SetPortPolar(__POLAR__) SFRX_ASSIGN(PWMA_CCER1, 3, (__POLAR__))
  145. #define PWMA_PWM2_SetPortState(__STATE__) SFRX_ASSIGN(PWMA_CCER1, 4, (__STATE__))
  146. #define PWMA_PWM2_SetPortPolar(__POLAR__) SFRX_ASSIGN(PWMA_CCER1, 5, (__POLAR__))
  147. #define PWMA_PWM2N_SetPortState(__STATE__) SFRX_ASSIGN(PWMA_CCER1, 6, (__STATE__))
  148. #define PWMA_PWM2N_SetPortPolar(__POLAR__) SFRX_ASSIGN(PWMA_CCER1, 7, (__POLAR__))
  149. #define PWMA_PWM3_SetPortState(__STATE__) SFRX_ASSIGN(PWMA_CCER2, 0, (__STATE__))
  150. #define PWMA_PWM3_SetPortPolar(__POLAR__) SFRX_ASSIGN(PWMA_CCER2, 1, (__POLAR__))
  151. #define PWMA_PWM3N_SetPortState(__STATE__) SFRX_ASSIGN(PWMA_CCER2, 2, (__STATE__))
  152. #define PWMA_PWM3N_SetPortPolar(__POLAR__) SFRX_ASSIGN(PWMA_CCER2, 3, (__POLAR__))
  153. #define PWMA_PWM4_SetPortState(__STATE__) SFRX_ASSIGN(PWMA_CCER2, 4, (__STATE__))
  154. #define PWMA_PWM4_SetPortPolar(__POLAR__) SFRX_ASSIGN(PWMA_CCER2, 5, (__POLAR__))
  155. #define PWMA_PWM4N_SetPortState(__STATE__) SFRX_ASSIGN(PWMA_CCER2, 6, (__STATE__))
  156. #define PWMA_PWM4N_SetPortPolar(__POLAR__) SFRX_ASSIGN(PWMA_CCER2, 7, (__POLAR__))
  157. /**
  158. * Configurate PWMA.1 - PWMA.4 port direction
  159. */
  160. typedef enum
  161. {
  162. PWMA_PortDirOut = 0x00,
  163. PWMA_PortDirIn_TI1FP1_TI2FP2_TI3FP3_TI4FP4 = 0x01,
  164. PWMA_PortDirIn_TI2FP1_TI1FP2_TI4FP3_TI3FP4 = 0x10,
  165. PWMA_PortDirInTRC = 0x11,
  166. } PWMA_PortDirection_t;
  167. #define PWMA_PWM1_SetPortDirection(__PORT_DIR__) do{ \
  168. SFRX_ON();(PWMA_CCMR1 = PWMA_CCMR1 & ~(0x03 << 0) | ((__PORT_DIR__) << 0)); SFRX_OFF(); \
  169. }while(0)
  170. #define PWMA_PWM2_SetPortDirection(__PORT_DIR__) do{ \
  171. SFRX_ON();(PWMA_CCMR2 = PWMA_CCMR2 & ~(0x03 << 0) | ((__PORT_DIR__) << 0)); SFRX_OFF(); \
  172. }while(0)
  173. #define PWMA_PWM3_SetPortDirection(__PORT_DIR__) do{ \
  174. SFRX_ON();(PWMA_CCMR3 = PWMA_CCMR3 & ~(0x03 << 0) | ((__PORT_DIR__) << 0)); SFRX_OFF(); \
  175. }while(0)
  176. #define PWMA_PWM4_SetPortDirection(__PORT_DIR__) do{ \
  177. SFRX_ON();(PWMA_CCMR4 = PWMA_CCMR4 & ~(0x03 << 0) | ((__PORT_DIR__) << 0)); SFRX_OFF(); \
  178. }while(0)
  179. /**
  180. * PWMA.1 - PWMA.4 comparison value preload OFF/ON
  181. * 0: New values will be written to PWMx_CCRx and take effect immediately
  182. * 1: New values will be written to shadow register and loaded to PWMx_CCRx on next update event
  183. */
  184. #define PWMA_PWM1_SetComparePreload(__STATE__) SFRX_ASSIGN(PWMA_CCMR1, 3, (__STATE__))
  185. #define PWMA_PWM2_SetComparePreload(__STATE__) SFRX_ASSIGN(PWMA_CCMR2, 3, (__STATE__))
  186. #define PWMA_PWM3_SetComparePreload(__STATE__) SFRX_ASSIGN(PWMA_CCMR3, 3, (__STATE__))
  187. #define PWMA_PWM4_SetComparePreload(__STATE__) SFRX_ASSIGN(PWMA_CCMR4, 3, (__STATE__))
  188. /**
  189. * Configurate PWMA.1 - PWMA.4 out mode
  190. */
  191. #define PWMA_PWM1_ConfigOutputMode(__MODE__) do{ \
  192. SFRX_ON();(PWMA_CCMR1 = PWMA_CCMR1 & ~(0x07 << 4) | ((__MODE__) << 4)); SFRX_OFF(); \
  193. }while(0)
  194. #define PWMA_PWM2_ConfigOutputMode(__MODE__) do{ \
  195. SFRX_ON();(PWMA_CCMR2 = PWMA_CCMR2 & ~(0x07 << 4) | ((__MODE__) << 4)); SFRX_OFF(); \
  196. }while(0)
  197. #define PWMA_PWM3_ConfigOutputMode(__MODE__) do{ \
  198. SFRX_ON();(PWMA_CCMR3 = PWMA_CCMR3 & ~(0x07 << 4) | ((__MODE__) << 4)); SFRX_OFF(); \
  199. }while(0)
  200. #define PWMA_PWM4_ConfigOutputMode(__MODE__) do{ \
  201. SFRX_ON();(PWMA_CCMR4 = PWMA_CCMR4 & ~(0x07 << 4) | ((__MODE__) << 4)); SFRX_OFF(); \
  202. }while(0)
  203. /**
  204. * Configurate PWMA.1 - PWMA.4 capture/comparison value, this will affect duty cycle
  205. */
  206. #define PWMA_PWM1_SetCaptureCompareValue(__16BIT_VAL__) do{ \
  207. SFRX_ON(); \
  208. (PWMA_CCR1H = ((__16BIT_VAL__) >> 8)); \
  209. (PWMA_CCR1L = ((__16BIT_VAL__) & 0xFF)); \
  210. SFRX_OFF(); \
  211. }while(0)
  212. #define PWMA_PWM2_SetCaptureCompareValue(__16BIT_VAL__) do{ \
  213. SFRX_ON(); \
  214. (PWMA_CCR2H = ((__16BIT_VAL__) >> 8)); \
  215. (PWMA_CCR2L = ((__16BIT_VAL__) & 0xFF)); \
  216. SFRX_OFF(); \
  217. }while(0)
  218. #define PWMA_PWM3_SetCaptureCompareValue(__16BIT_VAL__) do{ \
  219. SFRX_ON(); \
  220. (PWMA_CCR3H = ((__16BIT_VAL__) >> 8)); \
  221. (PWMA_CCR3L = ((__16BIT_VAL__) & 0xFF)); \
  222. SFRX_OFF(); \
  223. }while(0)
  224. #define PWMA_PWM4_SetCaptureCompareValue(__16BIT_VAL__) do{ \
  225. SFRX_ON(); \
  226. (PWMA_CCR4H = ((__16BIT_VAL__) >> 8)); \
  227. (PWMA_CCR4L = ((__16BIT_VAL__) & 0xFF)); \
  228. SFRX_OFF(); \
  229. }while(0)
  230. /**
  231. * PWM1 - PWM4 alternative ports
  232. */
  233. typedef enum
  234. {
  235. // PWM1P PWM1N
  236. PWMA_PWM1_AlterPort_P10_P11 = 0x00,
  237. PWMA_PWM1_AlterPort_P20_P21 = 0x01,
  238. PWMA_PWM1_AlterPort_P60_P61 = 0x10,
  239. } PWMA_PWM1_AlterPort_t;
  240. typedef enum
  241. {
  242. PWMA_PWM2_AlterPort_P12P54_P13 = 0x00,
  243. PWMA_PWM2_AlterPort_P22_P23 = 0x01,
  244. PWMA_PWM2_AlterPort_P62_P63 = 0x10,
  245. } PWMA_PWM2_AlterPort_t;
  246. typedef enum
  247. {
  248. PWMA_PWM3_AlterPort_P14_P15 = 0x00,
  249. PWMA_PWM3_AlterPort_P24_P25 = 0x01,
  250. PWMA_PWM3_AlterPort_P64_P65 = 0x10,
  251. } PWMA_PWM3_AlterPort_t;
  252. typedef enum
  253. {
  254. PWMA_PWM4_AlterPort_P16_P17 = 0x00,
  255. PWMA_PWM4_AlterPort_P26_P27 = 0x01,
  256. PWMA_PWM4_AlterPort_P66_P67 = 0x10,
  257. PWMA_PWM4_AlterPort_P34_P33 = 0x11,
  258. } PWMA_PWM4_AlterPort_t;
  259. // Alternative port selection
  260. #define PWMA_PWM1_SetPort(__ALTER_PORT__) do{ \
  261. SFRX_ON();(PWMA_PS = PWMA_PS & ~(0x03 << 0) | ((__ALTER_PORT__) << 0)); SFRX_OFF(); \
  262. }while(0)
  263. #define PWMA_PWM2_SetPort(__ALTER_PORT__) do{ \
  264. SFRX_ON();(PWMA_PS = PWMA_PS & ~(0x03 << 2) | ((__ALTER_PORT__) << 2)); SFRX_OFF(); \
  265. }while(0)
  266. #define PWMA_PWM3_SetPort(__ALTER_PORT__) do{ \
  267. SFRX_ON();(PWMA_PS = PWMA_PS & ~(0x03 << 4) | ((__ALTER_PORT__) << 4)); SFRX_OFF(); \
  268. }while(0)
  269. #define PWMA_PWM4_SetPort(__ALTER_PORT__) do{ \
  270. SFRX_ON();(PWMA_PS = PWMA_PS & ~(0x03 << 6) | ((__ALTER_PORT__) << 6)); SFRX_OFF(); \
  271. }while(0)
  272. /**************************************************************************** /
  273. * PWMB
  274. */
  275. /**
  276. * PWM clock prescaler
  277. *
  278. * side alignment:
  279. * Fpwm = SYSCLK / (PWMx_PSCR + 1) / (PWMx_ARR + 1)
  280. * central alignment:
  281. * Fpwm = SYSCLK / (PWMx_PSCR + 1) / PWMx_ARR / 2
  282. */
  283. #define PWMB_SetPrescaler(__16BIT_VAL__) do { \
  284. SFRX_ON(); \
  285. (PWMB_PSCRH = ((__16BIT_VAL__) >> 8)); \
  286. (PWMB_PSCRL = ((__16BIT_VAL__) & 0xFF)); \
  287. SFRX_OFF(); \
  288. }while(0)
  289. #define PWMB_SetPeriod(__16BIT_VAL__) do { \
  290. SFRX_ON(); \
  291. (PWMB_ARRH = ((__16BIT_VAL__) >> 8)); \
  292. (PWMB_ARRL = ((__16BIT_VAL__) & 0xFF)); \
  293. SFRX_OFF(); \
  294. }while(0)
  295. // PWMA all pins input/output OFF/ON
  296. #define PWMB_SetOverallState(__STATE__) SFRX_ASSIGN(PWMB_BKR, 7, (__STATE__))
  297. // PWMB Pins Output OFF/ON
  298. #define PWMB_SetPinOutputState(__PINS__, __STATE__) do { \
  299. SFRX_ON(); \
  300. PWMB_ENO = PWMB_ENO & ~(__PINS__) | (((__STATE__) & 0x01)? (__PINS__) : 0x00); \
  301. SFRX_OFF(); \
  302. } while(0)
  303. // Enable/Disable PWMB_BKR Control on Pins
  304. #define PWMB_SetPinBrakeControl(__PINS__, __STATE__) do { \
  305. SFRX_ON(); \
  306. PWMB_IOAUX = PWMB_IOAUX & ~(__PINS__) | (((__STATE__) & 0x01)? (__PINS__) : 0x00); \
  307. SFRX_OFF(); \
  308. } while(0)
  309. /**
  310. * 0: New period will be written to [PWMB_ARRH,PWMB_ARRL] and take effect immediately
  311. * 1: New period will be written to shadow register and loaded to [PWMB_ARRH,PWMB_ARRL] on next update event
  312. */
  313. #define PWMB_SetAutoReloadPreload(__STATE__) SFRX_ASSIGN(PWMB_CR1, 7, (__STATE__))
  314. /**
  315. * Turn off counter (call PWMB_SetCounterState()) before changing to different alignment
  316. */
  317. #define PWMB_SetEdgeAlignment(__ALIGN__) do{ \
  318. SFRX_ON();(PWMB_CR1 = PWMB_CR1 & ~(0x03 << 5) | ((__ALIGN__) << 5));SFRX_OFF(); \
  319. }while(0)
  320. /**
  321. * 0: count from 0 to [PWMB_ARRH,PWMB_ARRL], then send an event and restart from 0
  322. * 1: count from [PWMB_ARRH,PWMB_ARRL] to 0, then send an event and restart from [PWMB_ARRH,PWMB_ARRL]
  323. */
  324. #define PWMB_SetCounterDirection(__DIR__) SFRX_ASSIGN(PWMB_CR1, 4, (__DIR__))
  325. /**
  326. * 0: counter continues when update event occurs
  327. * 1: counter stops(reset CEN) when update event occurs
  328. */
  329. #define PWMB_SetCounterOnePulse(__STATE__) SFRX_ASSIGN(PWMB_CR1, 3, (__STATE__))
  330. /**
  331. * Work only when update events are enabled
  332. * 0: An interrupt will be triggered by these events: counter overflow(upwards or downwards), soft set UG, timer/controller updates
  333. * 1: An interrupt will be triggered(and set UIF=1) by counter overflow(upwards or downwards)
  334. */
  335. #define PWMB_SetUpdateEventSource(__STATE__) SFRX_ASSIGN(PWMB_CR1, 2, (__STATE__))
  336. /**
  337. * 0:enable update events, 1:disable update events
  338. */
  339. #define PWMB_SetNonUpdateEvent(__STATE__) SFRX_ASSIGN(PWMB_CR1, 1, (__STATE__))
  340. /**
  341. * 0:stop counter, 1:start counter
  342. */
  343. #define PWMB_SetCounterState(__STATE__) SFRX_ASSIGN(PWMB_CR1, 0, (__STATE__))
  344. /**
  345. * PWMB.1(PWM5) - PWMB.4(PWM8) io polar and on/off state
  346. */
  347. #define PWMB_PWM1_SetPortState(__STATE__) SFRX_ASSIGN(PWMB_CCER1, 0, (__STATE__))
  348. #define PWMB_PWM1_SetPortPolar(__POLAR__) SFRX_ASSIGN(PWMB_CCER1, 1, (__POLAR__))
  349. #define PWMB_PWM2_SetPortState(__STATE__) SFRX_ASSIGN(PWMB_CCER1, 4, (__STATE__))
  350. #define PWMB_PWM2_SetPortPolar(__POLAR__) SFRX_ASSIGN(PWMB_CCER1, 5, (__POLAR__))
  351. #define PWMB_PWM3_SetPortState(__STATE__) SFRX_ASSIGN(PWMB_CCER2, 0, (__STATE__))
  352. #define PWMB_PWM3_SetPortPolar(__POLAR__) SFRX_ASSIGN(PWMB_CCER2, 1, (__POLAR__))
  353. #define PWMB_PWM4_SetPortState(__STATE__) SFRX_ASSIGN(PWMB_CCER2, 4, (__STATE__))
  354. #define PWMB_PWM4_SetPortPolar(__POLAR__) SFRX_ASSIGN(PWMB_CCER2, 5, (__POLAR__))
  355. /**
  356. * Configurate PWMB.1(PWM5) - PWMB.4(PWM8) port direction
  357. */
  358. typedef enum
  359. {
  360. PWMB_PortDirOut = 0x00,
  361. PWMB_PortDirIn_TI5FP5_TI6FP6_TI7FP7_TI8FP8 = 0x01,
  362. PWMB_PortDirIn_TI6FP5_TI5FP6_TI8FP7_TI7FP8 = 0x10,
  363. PWMB_PortDirInTRC = 0x11,
  364. } PWMB_PortDirection_t;
  365. #define PWMB_PWM1_SetPortDirection(__PORT_DIR__) do{ \
  366. SFRX_ON();(PWMB_CCMR1 = PWMB_CCMR1 & ~(0x03 << 0) | ((__PORT_DIR__) << 0)); SFRX_OFF(); \
  367. }while(0)
  368. #define PWMB_PWM2_SetPortDirection(__PORT_DIR__) do{ \
  369. SFRX_ON();(PWMB_CCMR2 = PWMB_CCMR2 & ~(0x03 << 0) | ((__PORT_DIR__) << 0)); SFRX_OFF(); \
  370. }while(0)
  371. #define PWMB_PWM3_SetPortDirection(__PORT_DIR__) do{ \
  372. SFRX_ON();(PWMB_CCMR3 = PWMB_CCMR3 & ~(0x03 << 0) | ((__PORT_DIR__) << 0)); SFRX_OFF(); \
  373. }while(0)
  374. #define PWMB_PWM4_SetPortDirection(__PORT_DIR__) do{ \
  375. SFRX_ON();(PWMB_CCMR4 = PWMB_CCMR4 & ~(0x03 << 0) | ((__PORT_DIR__) << 0)); SFRX_OFF(); \
  376. }while(0)
  377. /**
  378. * PWMB.1 - PWMB.4 comparison value preload OFF/ON
  379. * 0: New values will be written to PWMx_CCRx and take effect immediately
  380. * 1: New values will be written to shadow register and loaded to PWMx_CCRx on next update event
  381. */
  382. #define PWMB_PWM1_SetComparePreload(__STATE__) SFRX_ASSIGN(PWMB_CCMR1, 3, (__STATE__))
  383. #define PWMB_PWM2_SetComparePreload(__STATE__) SFRX_ASSIGN(PWMB_CCMR2, 3, (__STATE__))
  384. #define PWMB_PWM3_SetComparePreload(__STATE__) SFRX_ASSIGN(PWMB_CCMR3, 3, (__STATE__))
  385. #define PWMB_PWM4_SetComparePreload(__STATE__) SFRX_ASSIGN(PWMB_CCMR4, 3, (__STATE__))
  386. /**
  387. * Configurate PWMB.1(PWM5) - PWMB.4(PWM8) output mode
  388. */
  389. #define PWMB_PWM1_ConfigOutputMode(__MODE__) do{ \
  390. SFRX_ON();(PWMB_CCMR1 = PWMB_CCMR1 & ~(0x07 << 4) | ((__MODE__) << 4)); SFRX_OFF(); \
  391. }while(0)
  392. #define PWMB_PWM2_ConfigOutputMode(__MODE__) do{ \
  393. SFRX_ON();(PWMB_CCMR2 = PWMB_CCMR2 & ~(0x07 << 4) | ((__MODE__) << 4)); SFRX_OFF(); \
  394. }while(0)
  395. #define PWMB_PWM3_ConfigOutputMode(__MODE__) do{ \
  396. SFRX_ON();(PWMB_CCMR3 = PWMB_CCMR3 & ~(0x07 << 4) | ((__MODE__) << 4)); SFRX_OFF(); \
  397. }while(0)
  398. #define PWMB_PWM4_ConfigOutputMode(__MODE__) do{ \
  399. SFRX_ON();(PWMB_CCMR4 = PWMB_CCMR4 & ~(0x07 << 4) | ((__MODE__) << 4)); SFRX_OFF(); \
  400. }while(0)
  401. /**
  402. * Configurate PWMB.1(PWM5) - PWMB.4(PWM8) capture/comparison value, this will affect duty cycle
  403. */
  404. #define PWMB_PWM1_SetCaptureCompareValue(__16BIT_VAL__) do{ \
  405. SFRX_ON(); \
  406. (PWMB_CCR5H = ((__16BIT_VAL__) >> 8)); \
  407. (PWMB_CCR5L = ((__16BIT_VAL__) & 0xFF)); \
  408. SFRX_OFF(); \
  409. }while(0)
  410. #define PWMB_PWM2_SetCaptureCompareValue(__16BIT_VAL__) do{ \
  411. SFRX_ON(); \
  412. (PWMB_CCR6H = ((__16BIT_VAL__) >> 8)); \
  413. (PWMB_CCR6L = ((__16BIT_VAL__) & 0xFF)); \
  414. SFRX_OFF(); \
  415. }while(0)
  416. #define PWMB_PWM3_SetCaptureCompareValue(__16BIT_VAL__) do{ \
  417. SFRX_ON(); \
  418. (PWMB_CCR7H = ((__16BIT_VAL__) >> 8)); \
  419. (PWMB_CCR7L = ((__16BIT_VAL__) & 0xFF)); \
  420. SFRX_OFF(); \
  421. }while(0)
  422. #define PWMB_PWM4_SetCaptureCompareValue(__16BIT_VAL__) do{ \
  423. SFRX_ON(); \
  424. (PWMB_CCR8H = ((__16BIT_VAL__) >> 8)); \
  425. (PWMB_CCR8L = ((__16BIT_VAL__) & 0xFF)); \
  426. SFRX_OFF(); \
  427. }while(0)
  428. typedef enum
  429. {
  430. PWMB_PWM5_AlterPort_P20 = 0x00,
  431. PWMB_PWM5_AlterPort_P17 = 0x01,
  432. PWMB_PWM5_AlterPort_P00 = 0x10,
  433. PWMB_PWM5_AlterPort_P74 = 0x11,
  434. } PWMB_PWM5_AlterPort_t;
  435. typedef enum
  436. {
  437. PWMB_PWM6_AlterPort_P21 = 0x00,
  438. PWMB_PWM6_AlterPort_P54 = 0x01,
  439. PWMB_PWM6_AlterPort_P01 = 0x10,
  440. PWMB_PWM6_AlterPort_P75 = 0x11,
  441. } PWMB_PWM6_AlterPort_t;
  442. typedef enum
  443. {
  444. PWMB_PWM7_AlterPort_P22 = 0x00,
  445. PWMB_PWM7_AlterPort_P33 = 0x01,
  446. PWMB_PWM7_AlterPort_P02 = 0x10,
  447. PWMB_PWM7_AlterPort_P76 = 0x11,
  448. } PWMB_PWM7_AlterPort_t;
  449. typedef enum
  450. {
  451. PWMB_PWM8_AlterPort_P23 = 0x00,
  452. PWMB_PWM8_AlterPort_P34 = 0x01,
  453. PWMB_PWM8_AlterPort_P03 = 0x10,
  454. PWMB_PWM8_AlterPort_P77 = 0x11,
  455. } PWMB_PWM8_AlterPort_t;
  456. // Alternative port selection
  457. #define PWMB_PWM1_SetPort(__ALTER_PORT__) do{ \
  458. SFRX_ON();(PWMB_PS = PWMB_PS & ~(0x03 << 0) | ((__ALTER_PORT__) << 0)); SFRX_OFF(); \
  459. }while(0)
  460. #define PWMB_PWM2_SetPort(__ALTER_PORT__) do{ \
  461. SFRX_ON();(PWMB_PS = PWMB_PS & ~(0x03 << 2) | ((__ALTER_PORT__) << 2)); SFRX_OFF(); \
  462. }while(0)
  463. #define PWMB_PWM3_SetPort(__ALTER_PORT__) do{ \
  464. SFRX_ON();(PWMB_PS = PWMB_PS & ~(0x03 << 4) | ((__ALTER_PORT__) << 4)); SFRX_OFF(); \
  465. }while(0)
  466. #define PWMB_PWM4_SetPort(__ALTER_PORT__) do{ \
  467. SFRX_ON();(PWMB_PS = PWMB_PS & ~(0x03 << 6) | ((__ALTER_PORT__) << 6)); SFRX_OFF(); \
  468. }while(0)
  469. #endif