ATY_LIB V2_102_230218
ATY_LIB for general devices or ALGO
 
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Macros | Functions
ci24r1.h File Reference
#include "fw_hal.h"
#include "string.h"

Go to the source code of this file.

Macros

#define CI24R1_PLOAD_WIDTH   16
 
#define CI24R1_CSN   P35
 
#define CI24R1_MOSI   P34
 
#define CI24R1_SCK   P32
 
#define CI24R1_DATA_OUT()   GPIO_P3_SetMode(GPIO_Pin_4, GPIO_Mode_Output_PP)
 
#define CI24R1_DATA_IN()   GPIO_P3_SetMode(GPIO_Pin_4, GPIO_Mode_Input_HIP)
 
#define CI24R1_DATA_LOW()   CI24R1_MOSI = 0
 
#define CI24R1_DATA_HIGH()   CI24R1_MOSI = 1
 
#define CI24R1_DATA_READ()   CI24R1_MOSI
 
#define CI24R1_CLK_LOW()   CI24R1_SCK = 0
 
#define CI24R1_CLK_HIGH()   CI24R1_SCK = 1
 
#define CI24R1_NSS_LOW()   CI24R1_CSN = 0
 
#define CI24R1_NSS_HIGH()   CI24R1_CSN = 1
 
#define CI24R1_CE_LOW()   CI24R1_WriteReg(CI24R1_CMD_CE_OFF, CI24R1_CMD_NOP)
 
#define CI24R1_CE_HIGH()   CI24R1_WriteReg(CI24R1_CMD_CE_ON, CI24R1_CMD_NOP)
 
#define CI24R1_CMD_R_REGISTER   0x00
 
#define CI24R1_CMD_W_REGISTER   0x20
 
#define CI24R1_CMD_R_RX_PAYLOAD   0x61
 
#define CI24R1_CMD_W_TX_PAYLOAD   0xA0
 
#define CI24R1_CMD_FLUSH_TX   0xE1
 
#define CI24R1_CMD_FLUSH_RX   0xE2
 
#define CI24R1_CMD_REUSE_TX_PL   0xE3
 
#define CI24R1_CMD_R_RX_PL_WID   0x60
 
#define CI24R1_CMD_W_ACK_PAYLOAD   0xA8
 
#define CI24R1_CMD_W_TX_PAYLOAD_NOACK   0xB0
 
#define CI24R1_CMD_NOP   0xFF
 
#define CI24R1_CMD_CE_ON   0x70
 
#define CI24R1_CMD_CE_OFF   0x71
 
#define CI24R1_CMD_SELSPI   0x74
 
#define CI24R1_CMD_SELIRQ   0x75
 
#define CI24R1_REG_CONFIG   0x00
 
#define CI24R1_REG_EN_AA   0x01
 
#define CI24R1_REG_EN_RXADDR   0x02
 
#define CI24R1_REG_SETUP_AW   0x03
 
#define CI24R1_REG_SETUP_RETR   0x04
 
#define CI24R1_REG_RF_CH   0x05
 
#define CI24R1_REG_RF_SETUP   0x06
 
#define CI24R1_REG_STATUS   0x07
 
#define CI24R1_REG_OBSERVE_TX   0x08
 
#define CI24R1_REG_RSSI   0x09
 
#define CI24R1_REG_RX_ADDR_P0   0x0A
 
#define CI24R1_REG_RX_ADDR_P1   0x0B
 
#define CI24R1_REG_RX_ADDR_P2   0x0C
 
#define CI24R1_REG_RX_ADDR_P3   0x0D
 
#define CI24R1_REG_RX_ADDR_P4   0x0E
 
#define CI24R1_REG_RX_ADDR_P5AF   0x0F
 
#define CI24R1_REG_TX_ADDR   0x10
 
#define CI24R1_REG_RX_PW_P0   0x11
 
#define CI24R1_REG_RX_PW_P1   0x12
 
#define CI24R1_REG_RX_PW_P2   0x13
 
#define CI24R1_REG_RX_PW_P3   0x14
 
#define CI24R1_REG_RX_PW_P4   0x15
 
#define CI24R1_REG_RX_PW_P5   0x16
 
#define CI24R1_REG_FIFO_STATUS   0x17
 
#define CI24R1_REG_DYNPD   0x1C
 
#define CI24R1_REG_FEATURE   0x1D
 
#define CI24R1_EN_RXADDR_P5   0x00
 
#define CI24R1_EN_RXADDR_CRC   0x01
 
#define CI24R1_EN_RXADDR_OSC_C   0x02
 
#define CI24R1_EN_RXADDR_BT   0x04
 
#define CI24R1_EN_RXADDR_BT_CRC_L   0x06
 
#define CI24R1_EN_RXADDR_BT_CRC_M   0x07
 
#define CI24R1_EN_RXADDR_BT_CRC_H   0x08
 
#define CI24R1_RF_SETUP_11DB   0x07
 
#define CI24R1_RF_SETUP_10DB   0x06
 
#define CI24R1_RF_SETUP_9DB   0x05
 
#define CI24R1_RF_SETUP_7DB   0x04
 
#define CI24R1_RF_SETUP_3DB   0x03
 
#define CI24R1_RF_SETUP__1DB   0x02
 
#define CI24R1_RF_SETUP__4DB   0x01
 
#define CI24R1_RF_SETUP__9DB   0x00
 
#define CI24R1_RF_SETUP_250K   0x20
 
#define CI24R1_RF_SETUP_1M   0x00
 
#define CI24R1_RF_SETUP_2M   0x08
 
#define CI24R1_FLAG_RX_READY   0x40
 
#define CI24R1_FLAG_TX_SENT   0x20
 
#define CI24R1_FLAG_MAX_RT   0x10
 
#define CI24R1_PLOAD_MAX_WIDTH   32
 
#define CI24R1_TEST_ADDR   "CI24R"
 

Functions

void CI24R1_WriteReg (uint8_t reg, uint8_t value)
 
uint8_t CI24R1_ReadReg (uint8_t reg)
 
void CI24R1_WriteFromBuf (uint8_t reg, const uint8_t *pBuf, uint8_t len)
 
void CI24R1_ReadToBuf (uint8_t reg, uint8_t *pBuf, uint8_t len)
 
uint8_t CI24R1_SPI_Test (void)
 
void CI24R1_Init (void)
 
void CI24R1_SetChannel (uint8_t channel)
 
void CI24R1_SetTxAddress (uint8_t *address)
 
void CI24R1_SetRxAddress (uint8_t *address)
 
void CI24R1_SetTxMode (void)
 
void CI24R1_SetRxMode (void)
 
uint8_t CI24R1_Tx (uint8_t *ucPayload, uint8_t length)
 
uint8_t CI24R1_Rx (void)
 
uint8_t CI24R1_ReadStatus (void)
 
uint8_t CI24R1_PrintStatus (void)
 

Macro Definition Documentation

◆ CI24R1_CE_HIGH

#define CI24R1_CE_HIGH ( )    CI24R1_WriteReg(CI24R1_CMD_CE_ON, CI24R1_CMD_NOP)

Definition at line 40 of file ci24r1.h.

◆ CI24R1_CE_LOW

#define CI24R1_CE_LOW ( )    CI24R1_WriteReg(CI24R1_CMD_CE_OFF, CI24R1_CMD_NOP)

Definition at line 39 of file ci24r1.h.

◆ CI24R1_CLK_HIGH

#define CI24R1_CLK_HIGH ( )    CI24R1_SCK = 1

Definition at line 34 of file ci24r1.h.

◆ CI24R1_CLK_LOW

#define CI24R1_CLK_LOW ( )    CI24R1_SCK = 0

Definition at line 33 of file ci24r1.h.

◆ CI24R1_CMD_CE_OFF

#define CI24R1_CMD_CE_OFF   0x71

Definition at line 58 of file ci24r1.h.

◆ CI24R1_CMD_CE_ON

#define CI24R1_CMD_CE_ON   0x70

Definition at line 57 of file ci24r1.h.

◆ CI24R1_CMD_FLUSH_RX

#define CI24R1_CMD_FLUSH_RX   0xE2

Definition at line 51 of file ci24r1.h.

◆ CI24R1_CMD_FLUSH_TX

#define CI24R1_CMD_FLUSH_TX   0xE1

Definition at line 50 of file ci24r1.h.

◆ CI24R1_CMD_NOP

#define CI24R1_CMD_NOP   0xFF

Definition at line 56 of file ci24r1.h.

◆ CI24R1_CMD_R_REGISTER

#define CI24R1_CMD_R_REGISTER   0x00

REGISTER TABLE

Definition at line 46 of file ci24r1.h.

◆ CI24R1_CMD_R_RX_PAYLOAD

#define CI24R1_CMD_R_RX_PAYLOAD   0x61

Definition at line 48 of file ci24r1.h.

◆ CI24R1_CMD_R_RX_PL_WID

#define CI24R1_CMD_R_RX_PL_WID   0x60

Definition at line 53 of file ci24r1.h.

◆ CI24R1_CMD_REUSE_TX_PL

#define CI24R1_CMD_REUSE_TX_PL   0xE3

Definition at line 52 of file ci24r1.h.

◆ CI24R1_CMD_SELIRQ

#define CI24R1_CMD_SELIRQ   0x75

Definition at line 60 of file ci24r1.h.

◆ CI24R1_CMD_SELSPI

#define CI24R1_CMD_SELSPI   0x74

Definition at line 59 of file ci24r1.h.

◆ CI24R1_CMD_W_ACK_PAYLOAD

#define CI24R1_CMD_W_ACK_PAYLOAD   0xA8

Definition at line 54 of file ci24r1.h.

◆ CI24R1_CMD_W_REGISTER

#define CI24R1_CMD_W_REGISTER   0x20

Definition at line 47 of file ci24r1.h.

◆ CI24R1_CMD_W_TX_PAYLOAD

#define CI24R1_CMD_W_TX_PAYLOAD   0xA0

Definition at line 49 of file ci24r1.h.

◆ CI24R1_CMD_W_TX_PAYLOAD_NOACK

#define CI24R1_CMD_W_TX_PAYLOAD_NOACK   0xB0

Definition at line 55 of file ci24r1.h.

◆ CI24R1_CSN

#define CI24R1_CSN   P35

Definition at line 23 of file ci24r1.h.

◆ CI24R1_DATA_HIGH

#define CI24R1_DATA_HIGH ( )    CI24R1_MOSI = 1

Definition at line 30 of file ci24r1.h.

◆ CI24R1_DATA_IN

#define CI24R1_DATA_IN ( )    GPIO_P3_SetMode(GPIO_Pin_4, GPIO_Mode_Input_HIP)

Definition at line 28 of file ci24r1.h.

◆ CI24R1_DATA_LOW

#define CI24R1_DATA_LOW ( )    CI24R1_MOSI = 0

Definition at line 29 of file ci24r1.h.

◆ CI24R1_DATA_OUT

#define CI24R1_DATA_OUT ( )    GPIO_P3_SetMode(GPIO_Pin_4, GPIO_Mode_Output_PP)

Definition at line 27 of file ci24r1.h.

◆ CI24R1_DATA_READ

#define CI24R1_DATA_READ ( )    CI24R1_MOSI

Definition at line 31 of file ci24r1.h.

◆ CI24R1_EN_RXADDR_BT

#define CI24R1_EN_RXADDR_BT   0x04

Definition at line 99 of file ci24r1.h.

◆ CI24R1_EN_RXADDR_BT_CRC_H

#define CI24R1_EN_RXADDR_BT_CRC_H   0x08

Definition at line 102 of file ci24r1.h.

◆ CI24R1_EN_RXADDR_BT_CRC_L

#define CI24R1_EN_RXADDR_BT_CRC_L   0x06

Definition at line 100 of file ci24r1.h.

◆ CI24R1_EN_RXADDR_BT_CRC_M

#define CI24R1_EN_RXADDR_BT_CRC_M   0x07

Definition at line 101 of file ci24r1.h.

◆ CI24R1_EN_RXADDR_CRC

#define CI24R1_EN_RXADDR_CRC   0x01

Definition at line 97 of file ci24r1.h.

◆ CI24R1_EN_RXADDR_OSC_C

#define CI24R1_EN_RXADDR_OSC_C   0x02

Definition at line 98 of file ci24r1.h.

◆ CI24R1_EN_RXADDR_P5

#define CI24R1_EN_RXADDR_P5   0x00

Definition at line 96 of file ci24r1.h.

◆ CI24R1_FLAG_MAX_RT

#define CI24R1_FLAG_MAX_RT   0x10

Definition at line 120 of file ci24r1.h.

◆ CI24R1_FLAG_RX_READY

#define CI24R1_FLAG_RX_READY   0x40

Definition at line 118 of file ci24r1.h.

◆ CI24R1_FLAG_TX_SENT

#define CI24R1_FLAG_TX_SENT   0x20

Definition at line 119 of file ci24r1.h.

◆ CI24R1_MOSI

#define CI24R1_MOSI   P34

Definition at line 24 of file ci24r1.h.

◆ CI24R1_NSS_HIGH

#define CI24R1_NSS_HIGH ( )    CI24R1_CSN = 1

Definition at line 37 of file ci24r1.h.

◆ CI24R1_NSS_LOW

#define CI24R1_NSS_LOW ( )    CI24R1_CSN = 0

Definition at line 36 of file ci24r1.h.

◆ CI24R1_PLOAD_MAX_WIDTH

#define CI24R1_PLOAD_MAX_WIDTH   32

Definition at line 122 of file ci24r1.h.

◆ CI24R1_PLOAD_WIDTH

#define CI24R1_PLOAD_WIDTH   16

Definition at line 21 of file ci24r1.h.

◆ CI24R1_REG_CONFIG

#define CI24R1_REG_CONFIG   0x00

Definition at line 63 of file ci24r1.h.

◆ CI24R1_REG_DYNPD

#define CI24R1_REG_DYNPD   0x1C

Definition at line 91 of file ci24r1.h.

◆ CI24R1_REG_EN_AA

#define CI24R1_REG_EN_AA   0x01

Definition at line 64 of file ci24r1.h.

◆ CI24R1_REG_EN_RXADDR

#define CI24R1_REG_EN_RXADDR   0x02

Definition at line 65 of file ci24r1.h.

◆ CI24R1_REG_FEATURE

#define CI24R1_REG_FEATURE   0x1D

Definition at line 92 of file ci24r1.h.

◆ CI24R1_REG_FIFO_STATUS

#define CI24R1_REG_FIFO_STATUS   0x17

Definition at line 90 of file ci24r1.h.

◆ CI24R1_REG_OBSERVE_TX

#define CI24R1_REG_OBSERVE_TX   0x08

Definition at line 71 of file ci24r1.h.

◆ CI24R1_REG_RF_CH

#define CI24R1_REG_RF_CH   0x05

Definition at line 68 of file ci24r1.h.

◆ CI24R1_REG_RF_SETUP

#define CI24R1_REG_RF_SETUP   0x06

Definition at line 69 of file ci24r1.h.

◆ CI24R1_REG_RSSI

#define CI24R1_REG_RSSI   0x09

Definition at line 72 of file ci24r1.h.

◆ CI24R1_REG_RX_ADDR_P0

#define CI24R1_REG_RX_ADDR_P0   0x0A

Definition at line 73 of file ci24r1.h.

◆ CI24R1_REG_RX_ADDR_P1

#define CI24R1_REG_RX_ADDR_P1   0x0B

Definition at line 74 of file ci24r1.h.

◆ CI24R1_REG_RX_ADDR_P2

#define CI24R1_REG_RX_ADDR_P2   0x0C

Definition at line 75 of file ci24r1.h.

◆ CI24R1_REG_RX_ADDR_P3

#define CI24R1_REG_RX_ADDR_P3   0x0D

Definition at line 76 of file ci24r1.h.

◆ CI24R1_REG_RX_ADDR_P4

#define CI24R1_REG_RX_ADDR_P4   0x0E

Definition at line 77 of file ci24r1.h.

◆ CI24R1_REG_RX_ADDR_P5AF

#define CI24R1_REG_RX_ADDR_P5AF   0x0F

Definition at line 78 of file ci24r1.h.

◆ CI24R1_REG_RX_PW_P0

#define CI24R1_REG_RX_PW_P0   0x11

Definition at line 84 of file ci24r1.h.

◆ CI24R1_REG_RX_PW_P1

#define CI24R1_REG_RX_PW_P1   0x12

Definition at line 85 of file ci24r1.h.

◆ CI24R1_REG_RX_PW_P2

#define CI24R1_REG_RX_PW_P2   0x13

Definition at line 86 of file ci24r1.h.

◆ CI24R1_REG_RX_PW_P3

#define CI24R1_REG_RX_PW_P3   0x14

Definition at line 87 of file ci24r1.h.

◆ CI24R1_REG_RX_PW_P4

#define CI24R1_REG_RX_PW_P4   0x15

Definition at line 88 of file ci24r1.h.

◆ CI24R1_REG_RX_PW_P5

#define CI24R1_REG_RX_PW_P5   0x16

Definition at line 89 of file ci24r1.h.

◆ CI24R1_REG_SETUP_AW

#define CI24R1_REG_SETUP_AW   0x03

Definition at line 66 of file ci24r1.h.

◆ CI24R1_REG_SETUP_RETR

#define CI24R1_REG_SETUP_RETR   0x04

Definition at line 67 of file ci24r1.h.

◆ CI24R1_REG_STATUS

#define CI24R1_REG_STATUS   0x07

Definition at line 70 of file ci24r1.h.

◆ CI24R1_REG_TX_ADDR

#define CI24R1_REG_TX_ADDR   0x10

Definition at line 83 of file ci24r1.h.

◆ CI24R1_RF_SETUP_10DB

#define CI24R1_RF_SETUP_10DB   0x06

Definition at line 105 of file ci24r1.h.

◆ CI24R1_RF_SETUP_11DB

#define CI24R1_RF_SETUP_11DB   0x07

Definition at line 104 of file ci24r1.h.

◆ CI24R1_RF_SETUP_1M

#define CI24R1_RF_SETUP_1M   0x00

Definition at line 114 of file ci24r1.h.

◆ CI24R1_RF_SETUP_250K

#define CI24R1_RF_SETUP_250K   0x20

Definition at line 113 of file ci24r1.h.

◆ CI24R1_RF_SETUP_2M

#define CI24R1_RF_SETUP_2M   0x08

Definition at line 115 of file ci24r1.h.

◆ CI24R1_RF_SETUP_3DB

#define CI24R1_RF_SETUP_3DB   0x03

Definition at line 108 of file ci24r1.h.

◆ CI24R1_RF_SETUP_7DB

#define CI24R1_RF_SETUP_7DB   0x04

Definition at line 107 of file ci24r1.h.

◆ CI24R1_RF_SETUP_9DB

#define CI24R1_RF_SETUP_9DB   0x05

Definition at line 106 of file ci24r1.h.

◆ CI24R1_RF_SETUP__1DB

#define CI24R1_RF_SETUP__1DB   0x02

Definition at line 109 of file ci24r1.h.

◆ CI24R1_RF_SETUP__4DB

#define CI24R1_RF_SETUP__4DB   0x01

Definition at line 110 of file ci24r1.h.

◆ CI24R1_RF_SETUP__9DB

#define CI24R1_RF_SETUP__9DB   0x00

Definition at line 111 of file ci24r1.h.

◆ CI24R1_SCK

#define CI24R1_SCK   P32

Definition at line 25 of file ci24r1.h.

◆ CI24R1_TEST_ADDR

#define CI24R1_TEST_ADDR   "CI24R"

Definition at line 123 of file ci24r1.h.

Function Documentation

◆ CI24R1_Init()

void CI24R1_Init ( void  )

Definition at line 163 of file ci24r1.c.

164{
165 CI24R1_CE_LOW();
166#if (CI24R1_PLOAD_WIDTH == 0)
167 // Enable dynamic payload length on pipe 0 and pipe 1
168 CI24R1_WriteReg(CI24R1_CMD_W_REGISTER | CI24R1_REG_DYNPD, 0x03);
169 CI24R1_WriteReg(CI24R1_CMD_W_REGISTER | CI24R1_REG_FEATURE, 0x07);
170#else
171 // Fixed payload length
172 CI24R1_WriteReg(CI24R1_CMD_W_REGISTER | CI24R1_REG_DYNPD, 0x00);
173 CI24R1_WriteReg(CI24R1_CMD_W_REGISTER | CI24R1_REG_FEATURE, 0x03);
174 // Length of pipe 0
175 CI24R1_WriteReg(CI24R1_CMD_W_REGISTER | CI24R1_REG_RX_PW_P0, CI24R1_PLOAD_WIDTH);
176 // Length of pipe 1
177 CI24R1_WriteReg(CI24R1_CMD_W_REGISTER | CI24R1_REG_RX_PW_P1, CI24R1_PLOAD_WIDTH);
178#endif
179 CI24R1_WriteReg(CI24R1_CMD_W_REGISTER | CI24R1_REG_CONFIG, 0x0E);
180 // Enable auto ack all pipes
181 CI24R1_WriteReg(CI24R1_CMD_W_REGISTER | CI24R1_REG_EN_AA, 0x3F);
182 // Enable all pipes
183 CI24R1_WriteReg(CI24R1_CMD_W_REGISTER | CI24R1_REG_EN_RXADDR, 0x3F);
184 // Address width, 0x1:3bytes, 0x02:4bytes, 0x3:5bytes
185 CI24R1_WriteReg(CI24R1_CMD_W_REGISTER | CI24R1_REG_SETUP_AW, 0x03);
186 // Resend 500us and 3 times. interval: 250us * ([0, 15] + 1), retries: [0, 15]
187 CI24R1_WriteReg(CI24R1_CMD_W_REGISTER | CI24R1_REG_SETUP_RETR, (0x01 << 4) | 0x03);
188 // RF Data Rate 250K 11db
189 CI24R1_WriteReg(CI24R1_CMD_W_REGISTER | CI24R1_REG_RF_SETUP, CI24R1_RF_SETUP_1M | CI24R1_RF_SETUP_11DB);
190 CI24R1_CE_HIGH();
191}
CI24R1_WriteReg
void CI24R1_WriteReg(uint8_t reg, uint8_t value)
Definition: ci24r1.c:66
CI24R1_REG_RX_PW_P1
#define CI24R1_REG_RX_PW_P1
Definition: ci24r1.h:85
CI24R1_REG_DYNPD
#define CI24R1_REG_DYNPD
Definition: ci24r1.h:91
CI24R1_PLOAD_WIDTH
#define CI24R1_PLOAD_WIDTH
Definition: ci24r1.h:21
CI24R1_RF_SETUP_11DB
#define CI24R1_RF_SETUP_11DB
Definition: ci24r1.h:104
CI24R1_REG_FEATURE
#define CI24R1_REG_FEATURE
Definition: ci24r1.h:92
CI24R1_CE_HIGH
#define CI24R1_CE_HIGH()
Definition: ci24r1.h:40
CI24R1_REG_SETUP_AW
#define CI24R1_REG_SETUP_AW
Definition: ci24r1.h:66
CI24R1_REG_EN_AA
#define CI24R1_REG_EN_AA
Definition: ci24r1.h:64
CI24R1_REG_SETUP_RETR
#define CI24R1_REG_SETUP_RETR
Definition: ci24r1.h:67
CI24R1_RF_SETUP_1M
#define CI24R1_RF_SETUP_1M
Definition: ci24r1.h:114
CI24R1_REG_RF_SETUP
#define CI24R1_REG_RF_SETUP
Definition: ci24r1.h:69
CI24R1_REG_RX_PW_P0
#define CI24R1_REG_RX_PW_P0
Definition: ci24r1.h:84
CI24R1_REG_EN_RXADDR
#define CI24R1_REG_EN_RXADDR
Definition: ci24r1.h:65
CI24R1_CE_LOW
#define CI24R1_CE_LOW()
Definition: ci24r1.h:39
CI24R1_CMD_W_REGISTER
#define CI24R1_CMD_W_REGISTER
Definition: ci24r1.h:47
CI24R1_REG_CONFIG
#define CI24R1_REG_CONFIG
Definition: ci24r1.h:63

◆ CI24R1_PrintStatus()

uint8_t CI24R1_PrintStatus ( void  )

Definition at line 269 of file ci24r1.c.

270{
271 uint8_t i, status;
272
273 UART1_TxString("[Config]");
274 UART1_TxHex(CI24R1_ReadReg(CI24R1_CMD_R_REGISTER | CI24R1_REG_CONFIG));
275
276 UART1_TxString(" [EN_AA]");
277 UART1_TxHex(CI24R1_ReadReg(CI24R1_CMD_R_REGISTER | CI24R1_REG_EN_AA));
278
279 UART1_TxString(" [EN_RxAddr]");
280 UART1_TxHex(CI24R1_ReadReg(CI24R1_CMD_R_REGISTER | CI24R1_REG_EN_RXADDR));
281
282 UART1_TxString(" [AddrWidth]");
283 UART1_TxHex(CI24R1_ReadReg(CI24R1_CMD_R_REGISTER | CI24R1_REG_SETUP_AW));
284
285 UART1_TxString(" [Retry]");
286 UART1_TxHex(CI24R1_ReadReg(CI24R1_CMD_R_REGISTER | CI24R1_REG_SETUP_RETR));
287
288 UART1_TxString("\r\n[RF_Channel]");
289 UART1_TxHex(CI24R1_ReadReg(CI24R1_CMD_R_REGISTER | CI24R1_REG_RF_CH));
290
291 UART1_TxString(" [RF_Setup]");
292 UART1_TxHex(CI24R1_ReadReg(CI24R1_CMD_R_REGISTER | CI24R1_REG_RF_SETUP));
293
294 UART1_TxString(" [Observe_Tx]");
295 UART1_TxHex(CI24R1_ReadReg(CI24R1_CMD_R_REGISTER | CI24R1_REG_OBSERVE_TX));
296
297 UART1_TxString(" [RSSI]");
298 UART1_TxHex(CI24R1_ReadReg(CI24R1_CMD_R_REGISTER | CI24R1_REG_RSSI));
299
300 UART1_TxString("\r\n[TxAddr] ");
301 CI24R1_ReadToBuf(CI24R1_CMD_R_REGISTER | CI24R1_REG_TX_ADDR, xbuf_data, 5);
302 for (i = 0; i < 5; i++) {
303 UART1_TxHex(*(xbuf_data + i));
304 }
305
306 UART1_TxString("\r\n[RxAddrP0]");
307 CI24R1_ReadToBuf(CI24R1_CMD_R_REGISTER | CI24R1_REG_RX_ADDR_P0, xbuf_data, 5);
308 for (i = 0; i < 5; i++) {
309 UART1_TxHex(*(xbuf_data + i));
310 }
311 UART1_TxString(" [RxAddrP1]");
312 CI24R1_ReadToBuf(CI24R1_CMD_R_REGISTER | CI24R1_REG_RX_ADDR_P1, xbuf_data, 5);
313 for (i = 0; i < 5; i++) {
314 UART1_TxHex(*(xbuf_data + i));
315 }
316 UART1_TxString(" [RxAddrP2]");
317 UART1_TxHex(CI24R1_ReadReg(CI24R1_CMD_R_REGISTER | CI24R1_REG_RX_ADDR_P2));
318 UART1_TxString(" [RxAddrP3]");
319 UART1_TxHex(CI24R1_ReadReg(CI24R1_CMD_R_REGISTER | CI24R1_REG_RX_ADDR_P3));
320 UART1_TxString(" [RxAddrP4]");
321 UART1_TxHex(CI24R1_ReadReg(CI24R1_CMD_R_REGISTER | CI24R1_REG_RX_ADDR_P4));
322 UART1_TxString(" [RxAddrP5]");
323 UART1_TxHex(CI24R1_ReadReg(CI24R1_CMD_R_REGISTER | CI24R1_REG_RX_ADDR_P5AF));
324
325 UART1_TxString("\r\n[0F_CRC]");
326 CI24R1_Switch1F_AF(CI24R1_EN_RXADDR_CRC);
327 UART1_TxHex(CI24R1_ReadReg(CI24R1_CMD_R_REGISTER | CI24R1_REG_RX_ADDR_P5AF));
328
329 UART1_TxString(" [0F_OSC_C]");
330 CI24R1_Switch1F_AF(CI24R1_EN_RXADDR_OSC_C);
331 UART1_TxHex(CI24R1_ReadReg(CI24R1_CMD_R_REGISTER | CI24R1_REG_RX_ADDR_P5AF));
332
333 UART1_TxString(" [0F_BT]");
334 CI24R1_Switch1F_AF(CI24R1_EN_RXADDR_BT);
335 UART1_TxHex(CI24R1_ReadReg(CI24R1_CMD_R_REGISTER | CI24R1_REG_RX_ADDR_P5AF));
336
337 UART1_TxString(" [0F_BT_CRC_L/M/H]");
338 CI24R1_Switch1F_AF(CI24R1_EN_RXADDR_BT_CRC_L);
339 UART1_TxHex(CI24R1_ReadReg(CI24R1_CMD_R_REGISTER | CI24R1_REG_RX_ADDR_P5AF));
340 CI24R1_Switch1F_AF(CI24R1_EN_RXADDR_BT_CRC_M);
341 UART1_TxHex(CI24R1_ReadReg(CI24R1_CMD_R_REGISTER | CI24R1_REG_RX_ADDR_P5AF));
342 CI24R1_Switch1F_AF(CI24R1_EN_RXADDR_BT_CRC_H);
343 UART1_TxHex(CI24R1_ReadReg(CI24R1_CMD_R_REGISTER | CI24R1_REG_RX_ADDR_P5AF));
344
345 UART1_TxString("\r\n[RX_PW_P0]");
346 UART1_TxHex(CI24R1_ReadReg(CI24R1_CMD_R_REGISTER | CI24R1_REG_RX_PW_P0));
347 UART1_TxString(" [RX_PW_P1]");
348 UART1_TxHex(CI24R1_ReadReg(CI24R1_CMD_R_REGISTER | CI24R1_REG_RX_PW_P1));
349 UART1_TxString(" [RX_PW_P2]");
350 UART1_TxHex(CI24R1_ReadReg(CI24R1_CMD_R_REGISTER | CI24R1_REG_RX_PW_P2));
351 UART1_TxString(" [RX_PW_P3]");
352 UART1_TxHex(CI24R1_ReadReg(CI24R1_CMD_R_REGISTER | CI24R1_REG_RX_PW_P3));
353 UART1_TxString(" [RX_PW_P4]");
354 UART1_TxHex(CI24R1_ReadReg(CI24R1_CMD_R_REGISTER | CI24R1_REG_RX_PW_P4));
355 UART1_TxString(" [RX_PW_P5]");
356 UART1_TxHex(CI24R1_ReadReg(CI24R1_CMD_R_REGISTER | CI24R1_REG_RX_PW_P5));
357
358 UART1_TxString("\r\n[FIFO_Status]");
359 UART1_TxHex(CI24R1_ReadReg(CI24R1_CMD_R_REGISTER | CI24R1_REG_FIFO_STATUS));
360
361 UART1_TxString(" [DynPloadWidth]");
362 UART1_TxHex(CI24R1_ReadReg(CI24R1_CMD_R_REGISTER | CI24R1_REG_DYNPD));
363
364 UART1_TxString(" [Feature]");
365 UART1_TxHex(CI24R1_ReadReg(CI24R1_CMD_R_REGISTER | CI24R1_REG_FEATURE));
366
367 status = CI24R1_ReadStatus();
368 UART1_TxString("\r\n[Status]");
369 UART1_TxHex(status);
370 UART1_TxString("\r\n\r\n");
371 return status;
372}
xbuf_data
uint8_t * xbuf_data
Definition: ci24r1.c:18
CI24R1_ReadStatus
uint8_t CI24R1_ReadStatus(void)
Definition: ci24r1.c:249
CI24R1_ReadReg
uint8_t CI24R1_ReadReg(uint8_t reg)
Definition: ci24r1.c:74
CI24R1_Switch1F_AF
void CI24R1_Switch1F_AF(uint8_t af)
Definition: ci24r1.c:254
CI24R1_ReadToBuf
void CI24R1_ReadToBuf(uint8_t reg, uint8_t *pBuf, uint8_t len)
Definition: ci24r1.c:103
CI24R1_EN_RXADDR_BT
#define CI24R1_EN_RXADDR_BT
Definition: ci24r1.h:99
CI24R1_CMD_R_REGISTER
#define CI24R1_CMD_R_REGISTER
Definition: ci24r1.h:46
CI24R1_REG_RSSI
#define CI24R1_REG_RSSI
Definition: ci24r1.h:72
CI24R1_REG_RX_PW_P5
#define CI24R1_REG_RX_PW_P5
Definition: ci24r1.h:89
CI24R1_REG_FIFO_STATUS
#define CI24R1_REG_FIFO_STATUS
Definition: ci24r1.h:90
CI24R1_REG_TX_ADDR
#define CI24R1_REG_TX_ADDR
Definition: ci24r1.h:83
CI24R1_EN_RXADDR_BT_CRC_M
#define CI24R1_EN_RXADDR_BT_CRC_M
Definition: ci24r1.h:101
CI24R1_EN_RXADDR_BT_CRC_H
#define CI24R1_EN_RXADDR_BT_CRC_H
Definition: ci24r1.h:102
CI24R1_REG_RX_PW_P4
#define CI24R1_REG_RX_PW_P4
Definition: ci24r1.h:88
CI24R1_REG_RX_ADDR_P2
#define CI24R1_REG_RX_ADDR_P2
Definition: ci24r1.h:75
CI24R1_REG_RX_ADDR_P1
#define CI24R1_REG_RX_ADDR_P1
Definition: ci24r1.h:74
CI24R1_REG_RX_ADDR_P3
#define CI24R1_REG_RX_ADDR_P3
Definition: ci24r1.h:76
CI24R1_REG_RX_PW_P2
#define CI24R1_REG_RX_PW_P2
Definition: ci24r1.h:86
CI24R1_REG_OBSERVE_TX
#define CI24R1_REG_OBSERVE_TX
Definition: ci24r1.h:71
CI24R1_EN_RXADDR_OSC_C
#define CI24R1_EN_RXADDR_OSC_C
Definition: ci24r1.h:98
CI24R1_REG_RF_CH
#define CI24R1_REG_RF_CH
Definition: ci24r1.h:68
CI24R1_EN_RXADDR_CRC
#define CI24R1_EN_RXADDR_CRC
Definition: ci24r1.h:97
CI24R1_REG_RX_ADDR_P4
#define CI24R1_REG_RX_ADDR_P4
Definition: ci24r1.h:77
CI24R1_REG_RX_ADDR_P0
#define CI24R1_REG_RX_ADDR_P0
Definition: ci24r1.h:73
CI24R1_EN_RXADDR_BT_CRC_L
#define CI24R1_EN_RXADDR_BT_CRC_L
Definition: ci24r1.h:100
CI24R1_REG_RX_PW_P3
#define CI24R1_REG_RX_PW_P3
Definition: ci24r1.h:87
CI24R1_REG_RX_ADDR_P5AF
#define CI24R1_REG_RX_ADDR_P5AF
Definition: ci24r1.h:78
uint8_t
unsigned char uint8_t
Definition: fw_types.h:18
UART1_TxString
void UART1_TxString(uint8_t *str)
Definition: fw_uart.c:85
UART1_TxHex
void UART1_TxHex(uint8_t hex)
Definition: fw_uart.c:79
i
uint8_t __XDATA i
Definition: mem_read_chipid.c:24

◆ CI24R1_ReadReg()

uint8_t CI24R1_ReadReg ( uint8_t  reg)

Definition at line 74 of file ci24r1.c.

75{
76 uint8_t reg_val;
77 CI24R1_NSS_LOW();
78 CI24R1_WriteByte(reg);
79 reg_val = CI24R1_ReadByte();
80 CI24R1_NSS_HIGH();
81 return reg_val;
82}
CI24R1_ReadByte
uint8_t CI24R1_ReadByte(void)
Definition: ci24r1.c:42
CI24R1_WriteByte
void CI24R1_WriteByte(uint8_t value)
Definition: ci24r1.c:20
CI24R1_NSS_LOW
#define CI24R1_NSS_LOW()
Definition: ci24r1.h:36
CI24R1_NSS_HIGH
#define CI24R1_NSS_HIGH()
Definition: ci24r1.h:37

◆ CI24R1_ReadStatus()

uint8_t CI24R1_ReadStatus ( void  )

Definition at line 249 of file ci24r1.c.

250{
251 return CI24R1_ReadReg(CI24R1_CMD_R_REGISTER | CI24R1_REG_STATUS);
252}
CI24R1_REG_STATUS
#define CI24R1_REG_STATUS
Definition: ci24r1.h:70

◆ CI24R1_ReadToBuf()

void CI24R1_ReadToBuf ( uint8_t  reg,
uint8_t *  pBuf,
uint8_t  len 
)

Definition at line 103 of file ci24r1.c.

104{
105 uint8_t ctr;
106 CI24R1_NSS_LOW();
107 CI24R1_WriteByte(reg);
108 for (ctr = 0; ctr < len; ctr++)
109 {
110 pBuf[ctr] = CI24R1_ReadByte();
111 }
112 CI24R1_NSS_HIGH();
113
114}

◆ CI24R1_Rx()

uint8_t CI24R1_Rx ( void  )

Definition at line 217 of file ci24r1.c.

218{
219 uint8_t i, status, rxplWidth;
220 CI24R1_WriteReg(CI24R1_CMD_FLUSH_RX, CI24R1_CMD_NOP);
221 CI24R1_WriteReg(CI24R1_CMD_SELIRQ, CI24R1_CMD_NOP);
222 CI24R1_DATA_IN();
223 while(CI24R1_DATA_READ());
224 CI24R1_DATA_OUT();
225 CI24R1_WriteReg(CI24R1_CMD_SELSPI, CI24R1_CMD_NOP);
226 status = CI24R1_ReadStatus();
227 UART1_TxChar('>');
228 UART1_TxHex(status);
229 if (status & CI24R1_FLAG_RX_READY)
230 {
231#if CI24R1_PLOAD_WIDTH == 0
232 rxplWidth = CI24R1_ReadReg(CI24R1_CMD_R_RX_PL_WID);
233#else
234 rxplWidth = CI24R1_PLOAD_WIDTH;
235#endif
236 // Read RX to buffer
237 CI24R1_ReadToBuf(CI24R1_CMD_R_RX_PAYLOAD, xbuf, rxplWidth);
238 // Clear status flags
239 CI24R1_WriteReg(CI24R1_CMD_W_REGISTER | CI24R1_REG_STATUS, status);
240 UART1_TxChar('>');
241 for (i = 0; i < rxplWidth; i++)
242 {
243 UART1_TxHex(*(xbuf_data + i));
244 }
245 }
246 return status;
247}
xbuf
__IDATA uint8_t xbuf[CI24R1_PLOAD_MAX_WIDTH+1]
Definition: ci24r1.c:17
CI24R1_DATA_IN
#define CI24R1_DATA_IN()
Definition: ci24r1.h:28
CI24R1_CMD_SELIRQ
#define CI24R1_CMD_SELIRQ
Definition: ci24r1.h:60
CI24R1_DATA_OUT
#define CI24R1_DATA_OUT()
Definition: ci24r1.h:27
CI24R1_FLAG_RX_READY
#define CI24R1_FLAG_RX_READY
Definition: ci24r1.h:118
CI24R1_CMD_NOP
#define CI24R1_CMD_NOP
Definition: ci24r1.h:56
CI24R1_DATA_READ
#define CI24R1_DATA_READ()
Definition: ci24r1.h:31
CI24R1_CMD_FLUSH_RX
#define CI24R1_CMD_FLUSH_RX
Definition: ci24r1.h:51
CI24R1_CMD_SELSPI
#define CI24R1_CMD_SELSPI
Definition: ci24r1.h:59
CI24R1_CMD_R_RX_PL_WID
#define CI24R1_CMD_R_RX_PL_WID
Definition: ci24r1.h:53
CI24R1_CMD_R_RX_PAYLOAD
#define CI24R1_CMD_R_RX_PAYLOAD
Definition: ci24r1.h:48
UART1_TxChar
void UART1_TxChar(char dat)
Definition: fw_uart.c:72

◆ CI24R1_SetChannel()

void CI24R1_SetChannel ( uint8_t  channel)

Definition at line 157 of file ci24r1.c.

158{
159 if (channel > 125) channel = 125;
160 CI24R1_WriteReg(CI24R1_CMD_W_REGISTER | CI24R1_REG_RF_CH, channel);
161}

◆ CI24R1_SetRxAddress()

void CI24R1_SetRxAddress ( uint8_t *  address)

Definition at line 152 of file ci24r1.c.

153{
154 CI24R1_WriteFromBuf(CI24R1_CMD_W_REGISTER | CI24R1_REG_RX_ADDR_P1, address, 5);
155}
CI24R1_WriteFromBuf
void CI24R1_WriteFromBuf(uint8_t reg, const uint8_t *pBuf, uint8_t len)
Definition: ci24r1.c:91

◆ CI24R1_SetRxMode()

void CI24R1_SetRxMode ( void  )

Definition at line 124 of file ci24r1.c.

125{
126 uint8_t value;
127 value = CI24R1_ReadReg(CI24R1_CMD_R_REGISTER | CI24R1_REG_CONFIG);
128 value |= 0x01;
129 CI24R1_WriteReg(CI24R1_CMD_W_REGISTER | CI24R1_REG_CONFIG, value);
130}
value
value
Definition: DS18B20_ATY.c:216

◆ CI24R1_SetTxAddress()

void CI24R1_SetTxAddress ( uint8_t *  address)

Definition at line 146 of file ci24r1.c.

147{
148 CI24R1_WriteFromBuf(CI24R1_CMD_W_REGISTER | CI24R1_REG_TX_ADDR, address, 5);
149 CI24R1_WriteFromBuf(CI24R1_CMD_W_REGISTER | CI24R1_REG_RX_ADDR_P0, address, 5);
150}

◆ CI24R1_SetTxMode()

void CI24R1_SetTxMode ( void  )

Definition at line 116 of file ci24r1.c.

117{
118 uint8_t value;
119 value = CI24R1_ReadReg(CI24R1_CMD_R_REGISTER | CI24R1_REG_CONFIG);
120 value &= 0xFE;
121 CI24R1_WriteReg(CI24R1_CMD_W_REGISTER | CI24R1_REG_CONFIG, value);
122}

◆ CI24R1_SPI_Test()

uint8_t CI24R1_SPI_Test ( void  )

Definition at line 132 of file ci24r1.c.

133{
134 uint8_t i, *ptr = (uint8_t *)CI24R1_TEST_ADDR;
135 CI24R1_CE_LOW();
136 CI24R1_WriteReg(CI24R1_CMD_SELSPI, CI24R1_CMD_NOP);
137 CI24R1_WriteFromBuf(CI24R1_CMD_W_REGISTER | CI24R1_REG_TX_ADDR, ptr, 5);
138 CI24R1_ReadToBuf(CI24R1_CMD_R_REGISTER | CI24R1_REG_TX_ADDR, xbuf, 5);
139 for (i = 0; i < 5; i++) {
140 UART1_TxHex(*(xbuf + i));
141 if (*(xbuf + i) != *ptr++) return HAL_ERROR;
142 }
143 return HAL_OK;
144}
CI24R1_TEST_ADDR
#define CI24R1_TEST_ADDR
Definition: ci24r1.h:123
HAL_ERROR
@ HAL_ERROR
Definition: fw_types.h:77
HAL_OK
@ HAL_OK
Definition: fw_types.h:76

◆ CI24R1_Tx()

uint8_t CI24R1_Tx ( uint8_t *  ucPayload,
uint8_t  length 
)

Definition at line 193 of file ci24r1.c.

194{
195 uint8_t status;
196#if (CI24R1_PLOAD_WIDTH == 0)
197 CI24R1_WriteFromBuf(CI24R1_CMD_W_TX_PAYLOAD, ucPayload, length);
198#else
199 CI24R1_WriteFromBuf(CI24R1_CMD_W_TX_PAYLOAD, ucPayload, CI24R1_PLOAD_WIDTH);
200#endif
201 CI24R1_CE_HIGH();
202 CI24R1_WriteCmd(CI24R1_CMD_SELIRQ);
203 CI24R1_DATA_IN();
204 while (CI24R1_DATA_READ());
205 CI24R1_DATA_OUT();
206 CI24R1_WriteCmd(CI24R1_CMD_SELSPI);
207 status = CI24R1_ReadStatus();
208 if (status & CI24R1_FLAG_MAX_RT)
209 {
210 CI24R1_WriteReg(CI24R1_CMD_FLUSH_TX, CI24R1_CMD_NOP);
211 }
212 // Clear status flags
213 CI24R1_WriteReg(CI24R1_CMD_W_REGISTER | CI24R1_REG_STATUS, status);
214 return status;
215}
CI24R1_WriteCmd
void CI24R1_WriteCmd(uint8_t cmd)
Definition: ci24r1.c:84
CI24R1_CMD_W_TX_PAYLOAD
#define CI24R1_CMD_W_TX_PAYLOAD
Definition: ci24r1.h:49
CI24R1_CMD_FLUSH_TX
#define CI24R1_CMD_FLUSH_TX
Definition: ci24r1.h:50
CI24R1_FLAG_MAX_RT
#define CI24R1_FLAG_MAX_RT
Definition: ci24r1.h:120

◆ CI24R1_WriteFromBuf()

void CI24R1_WriteFromBuf ( uint8_t  reg,
const uint8_t *  pBuf,
uint8_t  len 
)

Definition at line 91 of file ci24r1.c.

92{
93 uint8_t ctr;
94 CI24R1_NSS_LOW();
95 CI24R1_WriteByte(reg);
96 for (ctr = 0; ctr < len; ctr++)
97 {
98 CI24R1_WriteByte(*pBuf++);
99 }
100 CI24R1_NSS_HIGH();
101}

◆ CI24R1_WriteReg()

void CI24R1_WriteReg ( uint8_t  reg,
uint8_t  value 
)

Definition at line 66 of file ci24r1.c.

67{
68 CI24R1_NSS_LOW();
69 CI24R1_WriteByte(reg);
70 CI24R1_WriteByte(value);
71 CI24R1_NSS_HIGH();
72}