#include "fw_conf.h"
#include "fw_types.h"
Go to the source code of this file.
◆ IAP_ClearCmdFailFlag
| #define IAP_ClearCmdFailFlag |
( |
| ) |
SFR_RESET(IAP_CONTR, 4) |
◆ IAP_CmdErase
| #define IAP_CmdErase |
( |
|
__16BIT_ADDR__ | ) |
|
Value: do{ \
EA = 0; \
IAP_ADDRH = ((__16BIT_ADDR__) >> 8); \
IAP_ADDRL = ((__16BIT_ADDR__) & 0xFF); \
IAP_CMD = IAP_CMD & ~(0x03) | 0x03; \
IAP_TRIG = 0x5A; \
IAP_TRIG = 0xA5; \
NOP();NOP(); \
IAP_SetIdle(); \
EA = 1; \
}while(0)
Erase one section (512 bytes), set all bytes to 0xFF
Definition at line 98 of file fw_iap.h.
◆ IAP_CmdRead
| #define IAP_CmdRead |
( |
|
__16BIT_ADDR__ | ) |
|
Value: do{ \
EA = 0; \
IAP_ADDRH = ((__16BIT_ADDR__) >> 8); \
IAP_ADDRL = ((__16BIT_ADDR__) & 0xFF); \
IAP_CMD = IAP_CMD & ~(0x03) | 0x01; \
IAP_TRIG = 0x5A; \
IAP_TRIG = 0xA5; \
NOP();NOP(); \
IAP_SetIdle(); \
EA = 1; \
}while(0)
Read one byte
Definition at line 70 of file fw_iap.h.
◆ IAP_CmdWrite
| #define IAP_CmdWrite |
( |
|
__16BIT_ADDR__ | ) |
|
Value: do{ \
EA = 0; \
IAP_ADDRH = ((__16BIT_ADDR__) >> 8); \
IAP_ADDRL = ((__16BIT_ADDR__) & 0xFF); \
IAP_CMD = IAP_CMD & ~(0x03) | 0x02; \
IAP_TRIG = 0x5A; \
IAP_TRIG = 0xA5; \
NOP();NOP(); \
IAP_SetIdle(); \
EA = 1; \
}while(0)
Write one byte, 1->0 only
Definition at line 84 of file fw_iap.h.
◆ IAP_IsCmdFailed
| #define IAP_IsCmdFailed |
( |
| ) |
(IAP_CONTR & (0x01 << 4)) |
◆ IAP_ReadData
| #define IAP_ReadData |
( |
| ) |
(IAP_DATA) |
◆ IAP_SetEnabled
| #define IAP_SetEnabled |
( |
|
__STATE__ | ) |
SFR_ASSIGN(IAP_CONTR, 7, __STATE__) |
◆ IAP_SetIdle
| #define IAP_SetIdle |
( |
| ) |
(IAP_CMD = IAP_CMD & ~(0x03)) |
Set cmd to idle
Definition at line 65 of file fw_iap.h.
◆ IAP_SetRestartFrom
| #define IAP_SetRestartFrom |
( |
|
__FROM__ | ) |
SFR_ASSIGN(IAP_CONTR, 6, __FROM__) |
◆ IAP_SetWaitTime
◆ IAP_SoftReset
| #define IAP_SoftReset |
( |
| ) |
SFR_SET(IAP_CONTR, 5) |
◆ IAP_WriteData
| #define IAP_WriteData |
( |
|
__BYTE__ | ) |
(IAP_DATA = (__BYTE__)) |
◆ IAP_RestartFrom_t
EEPROM size and IAP address of different series
| LINE | SIZE | ADDR START | ADDR END |
| STC8G1K08 | 4K | 0x0000 | 0x0FFF |
| STC8G1K08-8Pin | 4K | 0x0000 | 0x0FFF |
| STC8G1K08A | 4K | 0x0000 | 0x0FFF |
| STC8G1K08T | 4K | 0x0000 | 0x0FFF |
| STC8G2K60S4 | 4K | 0x0000 | 0x0FFF |
| STC8G2K60S2 | 4K | 0x0000 | 0x0FFF |
| STC8H1K08 | 4K | 0x0000 | 0x0FFF |
| STC8H1K24 | 4K | 0x0000 | 0x0FFF |
| STC8H3K60S2 | 4K | 0x0000 | 0x0FFF |
| STC8H3K60S4 | 4K | 0x0000 | 0x0FFF |
| STC8H8K60U | 4K | 0x0000 | 0x0FFF |
| STC8G1K04 | 8K | 0x0000 | 0x1FFF |
| STC8H1K16 | 12K | 0x0000 | 0x2FFF |
| STC8H3K48S2 | 16K | 0x0000 | 0x3FFF |
| STC8H3K48S4 | 16K | 0x0000 | 0x3FFF |
| STC8H8K48U | 16K | 0x0000 | 0x3FFF |
| STC8G2K48S4 | 16K | 0x0000 | 0x3FFF |
| STC8G2K48S2 | 16K | 0x0000 | 0x3FFF |
| STC8H3K32S2 | 32K | 0x0000 | 0x7FFF |
| STC8H3K32S4 | 32K | 0x0000 | 0x7FFF |
| STC8H8K32U | 32K | 0x0000 | 0x7FFF |
| STC8G2K32S4 | 32K | 0x0000 | 0x7FFF |
| STC8G2K32S2 | 32K | 0x0000 | 0x7FFF |
| Enumerator |
|---|
| IAP_RestartFrom_UserCode | |
| IAP_RestartFrom_ISPCode | |
Definition at line 52 of file fw_iap.h.
53{
@ IAP_RestartFrom_UserCode
@ IAP_RestartFrom_ISPCode